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Thu, 11 Apr 2024 12:34:24 +0000 (GMT) X-AuditID: b6c32a38-8e1ff700000027ae-1d-6617d8d1b627 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id EC.95.19234.0D8D7166; Thu, 11 Apr 2024 21:34:24 +0900 (KST) Received: from sgsupark03 (unknown [10.252.69.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240411123424epsmtip1542d9c86fd41c04bbc7e5e8f7c69dddf~FOd9To7Zd2195321953epsmtip1l; Thu, 11 Apr 2024 12:34:24 +0000 (GMT) From: "Seongsu Park" To: "'Will Deacon'" Cc: , , , , "'Leem ChaeHoon'" , "'Gyeonggeon Choi'" , "'Soomin Cho'" , "'DaeRo Lee'" , "'kmasta'" In-Reply-To: <20240410161217.GB25225@willie-the-truck> Subject: RE: [PATCH v3] arm64: Cleanup __cpu_set_tcr_t0sz() Date: Thu, 11 Apr 2024 21:34:24 +0900 Message-ID: <09b201da8c0c$95e8d050$c1ba70f0$@samsung.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHvwI0HeBmtypRhXs739VRw5VSDqAF0l7xGAY3KgECxIIKTQA== Content-Language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJJsWRmVeSWpSXmKPExsWy7bCmru7FG+JpBndaWS3eL+thtNjUdp/R 4s/G3UwWX/4uZbbY9Pgaq8XlXXPYLJZev8hkMenHFkaL9s8vWC1a7pg6cHmsmbeG0WPnrLvs HptWdbJ5bF5S73Ho7AJWj8+b5ALYorJtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0t zJUU8hJzU22VXHwCdN0yc4AOU1IoS8wpBQoFJBYXK+nb2RTll5akKmTkF5fYKqUWpOQUmBXo FSfmFpfmpevlpZZYGRoYGJkCFSZkZyzuWsZWMEO54sOCeywNjIdluhg5OSQETCS+L2pm6mLk 4hAS2MEo8X9LAwuE84lR4su/WcxwzsWzv1lhWnou/IRq2cko8XTWfaiq54wSd/+vYAapYhPQ kfj2bQoLiC0ioCqx7+cGRpAiZoELTBKd548wgiQ4Bcwk5rw6B2YLC1hLXPu6FqyZBaih99cX JhCbV8BS4tm9fkYIW1Di5MwnYEOZBeQltr+dwwxxkoLEz6fLWCGWOUncWrCTFaJGRGJ2ZxvY dRICSzkk3m5+AtXgIvF8RjMbhC0s8er4FnYIW0riZX8blF0sse/LGqj6GokH8/ZA2fYSHc/a gI7gAFqgKbF+lz7ELj6Jd197WEHCEgK8Eh1tQhCmssS5rY4QpqTEnwV6EDM8JD5uX8o6gVFx FpK/ZiH5axaS+2chrFrAyLKKUSy1oDg3PbXYsMAEHtnJ+bmbGMFpVstiB+Pctx/0DjEycTAe YpTgYFYS4ZXWEk0T4k1JrKxKLcqPLyrNSS0+xGgKDOmJzFKiyfnARJ9XEm9oYmlgYmZkYmFs aWymJM575kpZqpBAemJJanZqakFqEUwfEwenVAOTnDv/Ie3Dj/n39Pywy2c4aD/pV8CLh0ev z9647+zzf/xMJjdKNr1Zu6uv1yNxfV5FuoYU/yw+jYux2Rwuk41Fnu8pqA68FdDTuPraYtX3 5y4mvHbcwnlBZK2Ii3Bl4rY3W+Q1D54p830U+VDL+q3NJQmJ9O1nk1M5V19oZbVsqShdW+ij NHU6b3f8ycXFT5Z9nCIeMWvFze/tmjMTTkf3VTbr6atuNJI2Sn33x+/R7Y2mPcldQfe/OGoc ti0PMlj5Ja72fmX6zquc+2erGN4vb9OwvNn0R+T7dvffXtXX4/8xTfjtKvLqpcmtli89n3cv Fdw68Xpt7rp3uWva+HoVpgQtii08287j03kq9FO0EktxRqKhFnNRcSIANvnRXzwEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42LZdlhJTvfCDfE0gwsPdSzeL+thtNjUdp/R 4s/G3UwWX/4uZbbY9Pgaq8XlXXPYLJZev8hkMenHFkaL9s8vWC1a7pg6cHmsmbeG0WPnrLvs HptWdbJ5bF5S73Ho7AJWj8+b5ALYorhsUlJzMstSi/TtErgyFnctYyuYoVzxYcE9lgbGwzJd jJwcEgImEj0XfjJ1MXJxCAlsZ5ToWHuNCSIhKdH+7jJLFyMHkC0scfhwMUTNU0aJZWdOsYHU sAnoSHz7NoUFxBYRUJXY93MDI4jNLHCDSeL7c1W4oU8+vQJLcAqYScx5dQ7MFhawlrj2dS0z iM0C1Nz76wvYYl4BS4ln9/oZIWxBiZMzn4AdwSygJ9G2EWq+vMT2t3OYIe5UkPj5dBkrxA1O ErcW7GSFqBGRmN3ZxjyBUXgWkkmzECbNQjJpFpKOBYwsqxhFUwuKc9NzkwsM9YoTc4tL89L1 kvNzNzGC40wraAfjsvV/9Q4xMnEwHmKU4GBWEuGV1hJNE+JNSaysSi3Kjy8qzUktPsQozcGi JM6rnNOZIiSQnliSmp2aWpBaBJNl4uCUamBaXstkckji10/5b1cun3LPsLgTnOJ37avO/jaV iUd2fbdpzU+9rt2aYWCr7veVr+TsnneVz1MSQrxeLzEpY+jPnTIz/2LbS2f1i/MLUrce4+M5 NimDy6pvSmfw8sad1ZHPLoQvmxFwynRW1x1GwTfbVLI89rGc6pDgcugXZnZZumDVBdW9Cp1v +kqa0rcwdu306ll597a7oWVDpNrn8yv29orej+SY8n7dhs0MLq83iC7e/C7hzbfsE4brHQLM zAXi3C40brs8c8O25cxfDW+x7etiylmcHCreeTao5pjJronqWvvNRDUenLn8rarTxTlcYa00 F0Pa9S9ic/I6Or9WnGx99WPj2wXnufPEmPqUWIozEg21mIuKEwH7ysE3IgMAAA== X-CMS-MailID: 20240411123424epcas1p332af61d4009555e32e277b70b31a411f X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240408024022epcas1p176f9509f6f85fd8dbfa2dd17067a8aee References: <20240408024016.490516-1-sgsu.park@samsung.com> <20240410161217.GB25225@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_053435_635813_4EE5C54B X-CRM114-Status: GOOD ( 35.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > > On Mon, Apr 08, 2024 at 11:40:16AM +0900, Seongsu Park wrote: > > In cpu_set_default_tcr_t0sz(), it is an error to shift TCR_T0SZ_OFFSET > > twice form TCR_T0SZ() and __cpu_set_tcr_t0sz(). > > Since TCR_T0SZ_OFFSET is 0, no error occurred. > > We need to clarify whether the parameter of __cpu_set_tcr_t0sz is a > > shifted value or an unshifted value. > > > > We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. > > This is necessary for consistency with TCR_T1SZ. > > Therefore, the parameter of __cpu_set_tcr_t0sz is clarified as a > > shifted value. > > This commit message needs reworking. I would suggest something like: > > The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and > encodes the virtual address space translated by TTBR0_EL1. When > updating the field (for example, because we are switching to/from > the idmap page-table), __cpu_set_tcr_t0sz() erroneously treats its > 't0sz' argument as unshifted, resulting in harmless but confusing > double shifts by 0 in the code. > > Remove the unnecessary shifts. > Thank you for great feedback. Please check title and description. If these are appropriate, I will write the same in v4. [Title] arm64: Cleanup __cpu_set_tcr_t0sz() [Description] The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encodes the virtual address space translated by TTBR0_EL1. When updating the field, for example because we are switching to/from the idmap page-table, __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted, resulting in harmless but confusing double shifts by 0 in the code. Therefore, Remove the unnecessary shifts. > > Co-developed-by: Leem ChaeHoon > > Signed-off-by: Leem ChaeHoon > > Co-developed-by: Gyeonggeon Choi > > Signed-off-by: Gyeonggeon Choi > > Co-developed-by: Soomin Cho > > Signed-off-by: Soomin Cho > > Co-developed-by: DaeRo Lee > > Signed-off-by: DaeRo Lee > > Co-developed-by: kmasta > > Signed-off-by: kmasta > > Signed-off-by: Seongsu Park > > Honestly, although it's great that you all meet up to look at the kernel, > this long list of credits is a little absurd for a trivial patch like this. > Please can you decide who did the most work and give them the credit? > Hopefully there will be future opportunities for you all to contribute! > Okay. I got it. In v4, I'll leave only Leem ChaeHoon and me. > > --- > > > > v2: > > - Condition is updated > > v3: > > - Commit message is updated > > - cpu_set_tcr_t0sz macro is added > > > > --- > > arch/arm64/include/asm/mmu_context.h | 7 ++++--- > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/include/asm/mmu_context.h > > b/arch/arm64/include/asm/mmu_context.h > > index c768d16b81a4..fb603ec7f61f 100644 > > --- a/arch/arm64/include/asm/mmu_context.h > > +++ b/arch/arm64/include/asm/mmu_context.h > > @@ -72,15 +72,16 @@ static inline void __cpu_set_tcr_t0sz(unsigned > > long t0sz) { > > unsigned long tcr = read_sysreg(tcr_el1); > > > > - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) > > + if ((tcr & TCR_T0SZ_MASK) == t0sz) > > return; > > > > tcr &= ~TCR_T0SZ_MASK; > > - tcr |= t0sz << TCR_T0SZ_OFFSET; > > + tcr |= t0sz; > > write_sysreg(tcr, tcr_el1); > > isb(); > > } > > > > +#define cpu_set_tcr_t0sz(t0sz) > __cpu_set_tcr_t0sz(TCR_T0SZ(t0sz)) > > #define cpu_set_default_tcr_t0sz() > __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) > > #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) > > > > @@ -134,7 +135,7 @@ static inline void cpu_install_ttbr0(phys_addr_t > > ttbr0, unsigned long t0sz) { > > cpu_set_reserved_ttbr0(); > > local_flush_tlb_all(); > > - __cpu_set_tcr_t0sz(t0sz); > > + cpu_set_tcr_t0sz(t0sz); > > Sorry, but this is wrong. Please have a look at how cpu_install_ttbr0() is > called; specifically how trans_pgd_idmap_page() sets up 't0sz'. > > So I don't think you should change cpu_install_ttbr0() at all and adding a > cpu_set_tcr_t0sz() macro which calls TCR_T0SZ on the 't0sz' argument is a > mistake. > > Will Oops. You're right. My mistake. In v4, I'll remove this. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 752A7633 for ; Thu, 11 Apr 2024 12:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712838873; cv=none; b=Q4mUnyyKJ0gECse2+r6GJ7yBJMODxhchr+So9Eby8VAGS+17qbp9db2X+wgpwx6QBaW8rI+sy10W69RI/nIC00ZKpMiUVw4QFcAC+MlxGrNi1Bd6i4K2M1+NqFpSNiIhYxJGSSGZwg1g+8cnvTLWUynCH5kNCoHvrt4E5VFDF6w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712838873; c=relaxed/simple; bh=CWuT0JYg/EjAXvaq2+5+8lvflEeg5Eg7XoxdIkmg4UY=; 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Thu, 11 Apr 2024 21:34:25 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas1p3.samsung.com (KnoxPortal) with ESMTPA id 20240411123424epcas1p332af61d4009555e32e277b70b31a411f~FOd9i_XzG1026910269epcas1p31; Thu, 11 Apr 2024 12:34:24 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20240411123424epsmtrp11c5c2666a03035a68eb521a38ed7fd91~FOd9hyXBe0037700377epsmtrp1N; Thu, 11 Apr 2024 12:34:24 +0000 (GMT) X-AuditID: b6c32a38-8e1ff700000027ae-1d-6617d8d1b627 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id EC.95.19234.0D8D7166; Thu, 11 Apr 2024 21:34:24 +0900 (KST) Received: from sgsupark03 (unknown [10.252.69.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240411123424epsmtip1542d9c86fd41c04bbc7e5e8f7c69dddf~FOd9To7Zd2195321953epsmtip1l; Thu, 11 Apr 2024 12:34:24 +0000 (GMT) From: "Seongsu Park" To: "'Will Deacon'" Cc: , , , , "'Leem ChaeHoon'" , "'Gyeonggeon Choi'" , "'Soomin Cho'" , "'DaeRo Lee'" , "'kmasta'" In-Reply-To: <20240410161217.GB25225@willie-the-truck> Subject: RE: [PATCH v3] arm64: Cleanup __cpu_set_tcr_t0sz() Date: Thu, 11 Apr 2024 21:34:24 +0900 Message-ID: <09b201da8c0c$95e8d050$c1ba70f0$@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHvwI0HeBmtypRhXs739VRw5VSDqAF0l7xGAY3KgECxIIKTQA== Content-Language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJJsWRmVeSWpSXmKPExsWy7bCmru7FG+JpBndaWS3eL+thtNjUdp/R 4s/G3UwWX/4uZbbY9Pgaq8XlXXPYLJZev8hkMenHFkaL9s8vWC1a7pg6cHmsmbeG0WPnrLvs HptWdbJ5bF5S73Ho7AJWj8+b5ALYorJtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0t zJUU8hJzU22VXHwCdN0yc4AOU1IoS8wpBQoFJBYXK+nb2RTll5akKmTkF5fYKqUWpOQUmBXo FSfmFpfmpevlpZZYGRoYGJkCFSZkZyzuWsZWMEO54sOCeywNjIdluhg5OSQETCS+L2pm6mLk 4hAS2MEo8X9LAwuE84lR4su/WcxwzsWzv1lhWnou/IRq2cko8XTWfaiq54wSd/+vYAapYhPQ kfj2bQoLiC0ioCqx7+cGRpAiZoELTBKd548wgiQ4Bcwk5rw6B2YLC1hLXPu6FqyZBaih99cX JhCbV8BS4tm9fkYIW1Di5MwnYEOZBeQltr+dwwxxkoLEz6fLWCGWOUncWrCTFaJGRGJ2ZxvY dRICSzkk3m5+AtXgIvF8RjMbhC0s8er4FnYIW0riZX8blF0sse/LGqj6GokH8/ZA2fYSHc/a gI7gAFqgKbF+lz7ELj6Jd197WEHCEgK8Eh1tQhCmssS5rY4QpqTEnwV6EDM8JD5uX8o6gVFx FpK/ZiH5axaS+2chrFrAyLKKUSy1oDg3PbXYsMAEHtnJ+bmbGMFpVstiB+Pctx/0DjEycTAe YpTgYFYS4ZXWEk0T4k1JrKxKLcqPLyrNSS0+xGgKDOmJzFKiyfnARJ9XEm9oYmlgYmZkYmFs aWymJM575kpZqpBAemJJanZqakFqEUwfEwenVAOTnDv/Ie3Dj/n39Pywy2c4aD/pV8CLh0ev z9647+zzf/xMJjdKNr1Zu6uv1yNxfV5FuoYU/yw+jYux2Rwuk41Fnu8pqA68FdDTuPraYtX3 5y4mvHbcwnlBZK2Ii3Bl4rY3W+Q1D54p830U+VDL+q3NJQmJ9O1nk1M5V19oZbVsqShdW+ij NHU6b3f8ycXFT5Z9nCIeMWvFze/tmjMTTkf3VTbr6atuNJI2Sn33x+/R7Y2mPcldQfe/OGoc ti0PMlj5Ja72fmX6zquc+2erGN4vb9OwvNn0R+T7dvffXtXX4/8xTfjtKvLqpcmtli89n3cv Fdw68Xpt7rp3uWva+HoVpgQtii08287j03kq9FO0EktxRqKhFnNRcSIANvnRXzwEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42LZdlhJTvfCDfE0gwsPdSzeL+thtNjUdp/R 4s/G3UwWX/4uZbbY9Pgaq8XlXXPYLJZev8hkMenHFkaL9s8vWC1a7pg6cHmsmbeG0WPnrLvs HptWdbJ5bF5S73Ho7AJWj8+b5ALYorhsUlJzMstSi/TtErgyFnctYyuYoVzxYcE9lgbGwzJd jJwcEgImEj0XfjJ1MXJxCAlsZ5ToWHuNCSIhKdH+7jJLFyMHkC0scfhwMUTNU0aJZWdOsYHU sAnoSHz7NoUFxBYRUJXY93MDI4jNLHCDSeL7c1W4oU8+vQJLcAqYScx5dQ7MFhawlrj2dS0z iM0C1Nz76wvYYl4BS4ln9/oZIWxBiZMzn4AdwSygJ9G2EWq+vMT2t3OYIe5UkPj5dBkrxA1O ErcW7GSFqBGRmN3ZxjyBUXgWkkmzECbNQjJpFpKOBYwsqxhFUwuKc9NzkwsM9YoTc4tL89L1 kvNzNzGC40wraAfjsvV/9Q4xMnEwHmKU4GBWEuGV1hJNE+JNSaysSi3Kjy8qzUktPsQozcGi JM6rnNOZIiSQnliSmp2aWpBaBJNl4uCUamBaXstkckji10/5b1cun3LPsLgTnOJ37avO/jaV iUd2fbdpzU+9rt2aYWCr7veVr+TsnneVz1MSQrxeLzEpY+jPnTIz/2LbS2f1i/MLUrce4+M5 NimDy6pvSmfw8sad1ZHPLoQvmxFwynRW1x1GwTfbVLI89rGc6pDgcugXZnZZumDVBdW9Cp1v +kqa0rcwdu306ll597a7oWVDpNrn8yv29orej+SY8n7dhs0MLq83iC7e/C7hzbfsE4brHQLM zAXi3C40brs8c8O25cxfDW+x7etiylmcHCreeTao5pjJronqWvvNRDUenLn8rarTxTlcYa00 F0Pa9S9ic/I6Or9WnGx99WPj2wXnufPEmPqUWIozEg21mIuKEwH7ysE3IgMAAA== X-CMS-MailID: 20240411123424epcas1p332af61d4009555e32e277b70b31a411f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240408024022epcas1p176f9509f6f85fd8dbfa2dd17067a8aee References: <20240408024016.490516-1-sgsu.park@samsung.com> <20240410161217.GB25225@willie-the-truck> > > On Mon, Apr 08, 2024 at 11:40:16AM +0900, Seongsu Park wrote: > > In cpu_set_default_tcr_t0sz(), it is an error to shift TCR_T0SZ_OFFSET > > twice form TCR_T0SZ() and __cpu_set_tcr_t0sz(). > > Since TCR_T0SZ_OFFSET is 0, no error occurred. > > We need to clarify whether the parameter of __cpu_set_tcr_t0sz is a > > shifted value or an unshifted value. > > > > We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. > > This is necessary for consistency with TCR_T1SZ. > > Therefore, the parameter of __cpu_set_tcr_t0sz is clarified as a > > shifted value. > > This commit message needs reworking. I would suggest something like: > > The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and > encodes the virtual address space translated by TTBR0_EL1. When > updating the field (for example, because we are switching to/from > the idmap page-table), __cpu_set_tcr_t0sz() erroneously treats its > 't0sz' argument as unshifted, resulting in harmless but confusing > double shifts by 0 in the code. > > Remove the unnecessary shifts. > Thank you for great feedback. Please check title and description. If these are appropriate, I will write the same in v4. [Title] arm64: Cleanup __cpu_set_tcr_t0sz() [Description] The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encodes the virtual address space translated by TTBR0_EL1. When updating the field, for example because we are switching to/from the idmap page-table, __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted, resulting in harmless but confusing double shifts by 0 in the code. Therefore, Remove the unnecessary shifts. > > Co-developed-by: Leem ChaeHoon > > Signed-off-by: Leem ChaeHoon > > Co-developed-by: Gyeonggeon Choi > > Signed-off-by: Gyeonggeon Choi > > Co-developed-by: Soomin Cho > > Signed-off-by: Soomin Cho > > Co-developed-by: DaeRo Lee > > Signed-off-by: DaeRo Lee > > Co-developed-by: kmasta > > Signed-off-by: kmasta > > Signed-off-by: Seongsu Park > > Honestly, although it's great that you all meet up to look at the kernel, > this long list of credits is a little absurd for a trivial patch like this. > Please can you decide who did the most work and give them the credit? > Hopefully there will be future opportunities for you all to contribute! > Okay. I got it. In v4, I'll leave only Leem ChaeHoon and me. > > --- > > > > v2: > > - Condition is updated > > v3: > > - Commit message is updated > > - cpu_set_tcr_t0sz macro is added > > > > --- > > arch/arm64/include/asm/mmu_context.h | 7 ++++--- > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/include/asm/mmu_context.h > > b/arch/arm64/include/asm/mmu_context.h > > index c768d16b81a4..fb603ec7f61f 100644 > > --- a/arch/arm64/include/asm/mmu_context.h > > +++ b/arch/arm64/include/asm/mmu_context.h > > @@ -72,15 +72,16 @@ static inline void __cpu_set_tcr_t0sz(unsigned > > long t0sz) { > > unsigned long tcr = read_sysreg(tcr_el1); > > > > - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) > > + if ((tcr & TCR_T0SZ_MASK) == t0sz) > > return; > > > > tcr &= ~TCR_T0SZ_MASK; > > - tcr |= t0sz << TCR_T0SZ_OFFSET; > > + tcr |= t0sz; > > write_sysreg(tcr, tcr_el1); > > isb(); > > } > > > > +#define cpu_set_tcr_t0sz(t0sz) > __cpu_set_tcr_t0sz(TCR_T0SZ(t0sz)) > > #define cpu_set_default_tcr_t0sz() > __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) > > #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) > > > > @@ -134,7 +135,7 @@ static inline void cpu_install_ttbr0(phys_addr_t > > ttbr0, unsigned long t0sz) { > > cpu_set_reserved_ttbr0(); > > local_flush_tlb_all(); > > - __cpu_set_tcr_t0sz(t0sz); > > + cpu_set_tcr_t0sz(t0sz); > > Sorry, but this is wrong. Please have a look at how cpu_install_ttbr0() is > called; specifically how trans_pgd_idmap_page() sets up 't0sz'. > > So I don't think you should change cpu_install_ttbr0() at all and adding a > cpu_set_tcr_t0sz() macro which calls TCR_T0SZ on the 't0sz' argument is a > mistake. > > Will Oops. You're right. My mistake. In v4, I'll remove this.