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[86.149.41.185]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb34e608sm4560214f8f.23.2026.09.11.01.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 01:33:50 -0700 (PDT) Message-ID: <0b06e405f03ff521efc55ef1964726c8d8a11476.camel@oss.qualcomm.com> Subject: Re: [PATCH 0/7] Register MPM under CPU cluster power domain to manage RPM notification From: Christopher Obbard To: sneh.mankad@oss.qualcomm.com Cc: andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org, robh@kernel.org, shawn.guo@linaro.org, tglx@kernel.org, Dmitry Baryshkov Date: Fri, 11 Sep 2026 09:33:49 +0100 In-Reply-To: <20260713-b4-shikra_lpm_addition-v1-0-3d858df2cbbf@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-10 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: X94GVIqg9aekt64sFgEOCGx2zmDRlYJd X-Proofpoint-ORIG-GUID: X94GVIqg9aekt64sFgEOCGx2zmDRlYJd X-Proofpoint-Spam-Info: AW1haW4tMjYwOTExMDExOSBTYWx0ZWRfX9iELw3v0CZos WH0Ow8eFLZSB0sEmIWHT4FCLawvtU5vDQx0wbzeACeJsTSGkI9TkHdLKcC0a1n9h/EaQdw4bMVs at6VpMeRylvA0e8DFsEB1gMI9BEIxOk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTExMDExOSBTYWx0ZWRfX8MyHYDgXLnjc U+rYENOToZjZ8jRQpu1ZC/GIrvtNaxWJDZh/A1ZH8qvdZeu1DBuEc1arGse0SLsu8luZ3HgkHfZ gOX3HKMSjYVPmlKMlkwcwJ9MhiMFhqFp7DF7ixSHKBraktnRtVqITt+ymfs8kW0fVK9N2MTAzKE zKDHaSdlGJ7h//XQnIOrWOFZXkkMm8Fe80FCA4gkTcC44vwTi4JI61NIQ1z03zBhpdozT796ICG qQPWxvHvc/E54VnnKu5Y4OyjHbnrGC9eCbFfDzWWjIyFl2QkzDcswehhYcN0A3PAHg+n71oVtLY IqkG4tLXVGqnzdOjW4a/lTj/HlQ3WIRyGQTne9Deag+M9Rls1oVArap0Z39oN8l4d5e3SY/TB1M ADWqWPNd96JADrcOuuyNr3MWgW6H79mEX5LzwxBjyUZKxNDm5yzc3pXs8U7jHZzo4MGKJk5rekh Ghh/NKw19oMp8/4j8IQ== X-Authority-Analysis: v=2.4 cv=db0VTnXe c=1 sm=1 tr=0 ts=6aa3bcf5 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=1ZqYAqmp+mGnO5v9BrvPnw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=hY6swonQLBBWNHD_PR8A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-11_03,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609110119 Hi Sneh, > MPM irqchip needs to notify RPM (Resource Power Manager) processor to rea= d > the latest wake up capable interrupts when the CPU cluster is entering th= e > deepest idle state. This is done by sending IPC interrupt to RPM and is > implemented as .power_off() callback by registering MPM as parent power > domain to CPU cluster. >=20 > Such implementation introduces a hard probe dependency between MPM irqchi= p > and CPU cluster power domains. That is MPM irqchip needs to finish probe > before PSCI power domains are probed. MPM irqchip can be build as module > and can get later inserted where as PSCI power domains is not a module. >=20 > For in-built driver cases too PSCI domain gets probed first and later MPM > irqchip leading to failure of CPUidle states. ..snip.. > commit af5376a77e87 ("cpuidle: psci: Transition to the faux device > interface") transitioned cpuidle-psci to a faux device interface. >=20 > faux_device_create() calls faux_device_create_with_groups(), which ignore= s > the probe return value, and destroys the device if dev->driver is not set= . This is no longer true, see Commit 0606f2114e2d ("cpuidle: psci: Fix support for probe deferral by dropping the faux device"). ..snip.. > Currently only 2 SoCs follow this method - Agatti and sm6375. Agatti has > CPU cluster power domain disabled, which is why idle-states are allowed t= o > function there. Please don't forget about the devices which use the SoC: For Agatti, the RB1 (qrb2210-rb1) and Arduino UnoQ (qrb2210-arduino-imola) are both setup with different power domains (off-topic: I believe this is something which can be reworked soon as the mpm driver could be in a better place than before? Didn't check.). > Move the RPM notification handling to the GENPD_NOTIFY_PRE_OFF callback a= nd > register MPM under the CPU cluster power domain. Use runtime PM to repor= t > the default RPM_SUSPENDED state to genPD so that the CPU cluster power > domain can enter low power mode. >=20 > This will remove the dependency on probe ordering and allow individual CP= U > idle states, CPU cluster idle states and RPM notification to function > properly. >=20 > Also enable CPU and CPU cluster LPMs for Shikra. >=20 > Signed-off-by: Sneh Mankad > --- > Sneh Mankad (7): > dt-bindings: interrupt-controller: mpm: Document power-domains prop= erty > irqchip/irq-qcom-mpm: Register MPM under CPU cluster power domain > irqchip/irq-qcom-mpm: Prepare common access path for timer and pin = regs > irqchip/irq-qcom-mpm: Program wakeup timer when CPU cluster goes to= LPM > arm64: dts: qcom: sm6375: Make MPM device as part of CPU cluster do= main > arm64: dts: qcom: agatti: Do not mark MPM as power domain > arm64: dts: qcom: shikra: Add CPU idle states I also noticed that patches 2 and 6 are a matched pair but sit four patches apart. Every commit in between leaves Agatti device with no working CPU idle and e.g. a bisect can land inside that window. Can you move the DTS changes first? Cheers! Chris