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Wed, 12 Mar 2025 04:12:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CE5.mail.protection.outlook.com (10.167.242.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8534.20 via Frontend Transport; Wed, 12 Mar 2025 04:12:42 +0000 Received: from [10.252.206.76] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 11 Mar 2025 23:12:38 -0500 Message-ID: <0be5765e-2ade-4743-a089-0846f60943dd@amd.com> Date: Wed, 12 Mar 2025 09:42:31 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/6] amd_iommu: Update bitmasks representing DTE reserved fields To: Alejandro Jimenez , CC: , , , , , , , , , References: <20250311152446.45086-1-alejandro.j.jimenez@oracle.com> <20250311152446.45086-4-alejandro.j.jimenez@oracle.com> Content-Language: en-US From: "Arun Kodilkar, Sairaj" In-Reply-To: <20250311152446.45086-4-alejandro.j.jimenez@oracle.com> Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2025 04:12:42.7499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b486e40-6859-449c-a07d-08dd611c22e7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9086 Received-SPF: permerror client-ip=40.107.236.60; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Alejandro, On 3/11/2025 8:54 PM, Alejandro Jimenez wrote: > The DTE validation method verifies that all bits in reserved DTE fields are > unset. Update them according to the latest definition available in AMD I/O > Virtualization Technology (IOMMU) Specification - Section 2.2.2.1 Device > Table Entry Format. Remove the magic numbers and use a macro helper to > generate bitmasks covering the specified ranges for better legibility. > > Note that some reserved fields specify that events are generated when they > contain non-zero bits, or checks are skipped under certain configurations. > This change only updates the reserved masks, checks for special conditions > are not yet implemented. > > Cc: qemu-stable@nongnu.org > Signed-off-by: Alejandro Jimenez > --- > hw/i386/amd_iommu.c | 7 ++++--- > hw/i386/amd_iommu.h | 9 ++++++--- > 2 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 068eeb0cae..8b97abe28c 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -848,9 +848,10 @@ static inline uint64_t amdvi_get_perms(uint64_t entry) > static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid, > uint64_t *dte) > { > - if ((dte[0] & AMDVI_DTE_LOWER_QUAD_RESERVED) > - || (dte[1] & AMDVI_DTE_MIDDLE_QUAD_RESERVED) > - || (dte[2] & AMDVI_DTE_UPPER_QUAD_RESERVED) || dte[3]) { > + if ((dte[0] & AMDVI_DTE_QUAD0_RESERVED) || > + (dte[1] & AMDVI_DTE_QUAD1_RESERVED) || > + (dte[2] & AMDVI_DTE_QUAD2_RESERVED) || > + (dte[3] & AMDVI_DTE_QUAD3_RESERVED)) { > amdvi_log_illegaldevtab_error(s, devid, > s->devtab + > devid * AMDVI_DEVTAB_ENTRY_SIZE, 0); > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index 4c708f8d74..8d5d882a06 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -25,6 +25,8 @@ > #include "hw/i386/x86-iommu.h" > #include "qom/object.h" > > +#define GENMASK64(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) > + qemu provides the similar macro 'MAKE_64BIT_MASK' in file 'include/qemu/bitops.h', you can use this existing macro instead of redefining. > /* Capability registers */ > #define AMDVI_CAPAB_BAR_LOW 0x04 > #define AMDVI_CAPAB_BAR_HIGH 0x08 > @@ -162,9 +164,10 @@ > #define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */ > > /* reserved DTE bits */ > -#define AMDVI_DTE_LOWER_QUAD_RESERVED 0x80300000000000fc > -#define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100 > -#define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000 > +#define AMDVI_DTE_QUAD0_RESERVED (GENMASK64(6, 2) | GENMASK64(63, 63)) > +#define AMDVI_DTE_QUAD1_RESERVED 0 > +#define AMDVI_DTE_QUAD2_RESERVED GENMASK64(53, 52) > +#define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48)) > > /* AMDVI paging mode */ > #define AMDVI_GATS_MODE (2ULL << 12) Regards Sairaj Kodilkar