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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by MWH0EPF000A6732.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Wed, 9 Sep 2026 01:28:20 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 8 Sep 2026 20:28:20 -0500 Received: from [192.168.0.101] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Tue, 8 Sep 2026 20:28:15 -0500 Message-ID: <0c7c7902-e944-4c93-8188-6ca2f90b6795@amd.com> Date: Wed, 9 Sep 2026 06:58:14 +0530 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] perf/x86: Disable precise sampling for PERF_SAMPLE_STACK_USER To: "Mi, Dapeng" , Ian Rogers CC: Peter Zijlstra , Andi Kleen , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Adrian Hunter , Alexander Shishkin , Eranian Stephane , , , Dapeng Mi , "Zide Chen" , Falcon Thomas , "Xudong Hao" , Gennady Kupava , "Ravi Bangoria" References: <20260908075102.540715-1-dapeng1.mi@linux.intel.com> <20260908075102.540715-2-dapeng1.mi@linux.intel.com> <20260908084906.GO4121339@noisy.programming.kicks-ass.net> <1691a05c-49a6-4b16-8bad-cb3c004ed07c@linux.intel.com> <20260908101914.GQ4121339@noisy.programming.kicks-ass.net> Content-Language: en-US From: Ravi Bangoria In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QTI2s8/aTkPCjFgvw6NBNqpKvWnco8zd0G1VciEerj/2J5zx9ZQ9KLRWaDj7tgYVNssc1xhzZuH2HM1YhcBY7eqDAclxXozcS/3i6jdNaQvucy8kaqw5cgH2LFvgOTTM5VSvojqllWgshCK91EgaewVQ9WmwKaRQAmPE4BIvNuceJMi0v9V7phLQNsy/YHzl+UtHA+7WlugUt/3p7aIu1G7EtyOQ/LFmthrBPshj0z1HUmXCRv2D4G6v2xaP+/HKQkZXJsBJH7klZSPc4NNXgRvwq/7xdpKukqJIBigCLzFzyVkPT06piBV7tb/To+ELTDTMkhk6ywBQAkn0wHRZe6RQ9+Z0WkaWbb4hdMxegLsurcvVJYJ8SeHDLHhQ2ZHJrGzpKPs/m5aSioqZKXb8eelCgST05zDraXsbNCZrBHQ1zey3E/T1JHgOP0/k4SwJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2026 01:28:20.9367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b494c03b-d53d-41df-c583-08df0e11a24e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4159 >> Having PERF_SAMPLE_IP be precise and the user registers from the >> interrupt I believe works for AMD IBS and ARM SPE, but for Intel PEBS >> there is the ability to use the PEBS register samples for other >> non-redundant registers. In the x86 driver could we disable PEBS >> sampling for these registers when doing user stack sampling, so that >> the sampled user registers match the stack sample? We can keep the >> PERF_SAMPLE_IP precise, and make all the registers precise when there >> is no stack sampling. > > That sounds the best way to fix this issue by decoupling PERF_SAMPLE_IP > with PERF_REG_X86_IP. Then we can keep the precise SAMPLE_IP and the PMI > context user register snapshot simultaneously. With this, PERF_SAMPLE_IP and PERF_REG_X86_IP might be from different privileges. So, any perf code that depends on user_mode(regs) (e.g. perf_exclude_event(), _REGS_USER, _REGS_INTR, header->misc, etc.) also needs to be inspected/modified accordingly. Thanks, Ravi