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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4835dd20519sm207781085e9.15.2026.02.12.06.27.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Feb 2026 06:27:33 -0800 (PST) Message-ID: <0cd3bc01-7213-4cc5-996f-e8a518ffd0a3@redhat.com> Date: Thu, 12 Feb 2026 15:27:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/24] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, clg@redhat.com, alex@shazbot.org, nicolinc@nvidia.com, nathanc@nvidia.com, mochs@nvidia.com, jan@nvidia.com, jgg@nvidia.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, kjaju@nvidia.com References: <20260206144823.80655-1-skolothumtho@nvidia.com> <20260206144823.80655-7-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20260206144823.80655-7-skolothumtho@nvidia.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: o5tgwQVcCMLel-bYejjwFDzadIWEgtIC8ya5-Hs9ttk_1770906455 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Hi Shameer, On 2/6/26 3:48 PM, Shameer Kolothum wrote: > Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated > CMDQV ops interface. > > This patch wires up the Tegra241 CMDQV backend and provides a stub > implementation for CMDQV initialization, vIOMMU/vEVENTQ allocation > and reset handling. > > Functional CMDQV support is added in follow-up patches. > > Signed-off-by: Shameer Kolothum > --- > hw/arm/Kconfig | 5 ++++ > hw/arm/meson.build | 1 + > hw/arm/tegra241-cmdqv.c | 60 +++++++++++++++++++++++++++++++++++++++++ > hw/arm/tegra241-cmdqv.h | 23 ++++++++++++++++ > 4 files changed, 89 insertions(+) > create mode 100644 hw/arm/tegra241-cmdqv.c > create mode 100644 hw/arm/tegra241-cmdqv.h > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index c66c452737..3305c6e76e 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -626,6 +626,10 @@ config FSL_IMX8MP_EVK > depends on TCG > select FSL_IMX8MP > > +config TEGRA241_CMDQV > + bool > + depends on ARM_SMMUV3_ACCEL > + > config ARM_SMMUV3_ACCEL > bool > depends on ARM_SMMUV3 > @@ -633,6 +637,7 @@ config ARM_SMMUV3_ACCEL > config ARM_SMMUV3 > bool > select ARM_SMMUV3_ACCEL if IOMMUFD > + imply TEGRA241_CMDQV > > config FSL_IMX6UL > bool > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index c250487e64..4ec91db50a 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -86,6 +86,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c')) > arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) > arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c')) > +arm_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-cmdqv.c')) > arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) > arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) > arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( > diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c > new file mode 100644 > index 0000000000..6f30ca035b > --- /dev/null > +++ b/hw/arm/tegra241-cmdqv.c > @@ -0,0 +1,60 @@ > +/* > + * Copyright (C) 2025, NVIDIA CORPORATION > + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 > + * > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/arm/smmuv3.h" > +#include "smmuv3-accel.h" > +#include "tegra241-cmdqv.h" > + > +static void tegra241_cmdqv_free_veventq(SMMUv3State *s) > +{ > +} > + > +static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) > +{ > + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); > + return false; > +} > + > +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) > +{ > +} > + > +static bool > +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, > + uint32_t *out_viommu_id, Error **errp) > +{ > + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); > + return false; > +} > + > +static void tegra241_cmdqv_reset(SMMUv3State *s) > +{ > +} > + > +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) > +{ > + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); > + return false; > +} > + > +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops_impl = { > + .init = tegra241_cmdqv_init, > + .alloc_viommu = tegra241_cmdqv_alloc_viommu, > + .free_viommu = tegra241_cmdqv_free_viommu, > + .alloc_veventq = tegra241_cmdqv_alloc_veventq, > + .free_veventq = tegra241_cmdqv_free_veventq, > + .reset = tegra241_cmdqv_reset, > +}; > + > +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void) > +{ > + return &tegra241_cmdqv_ops_impl; > +} > diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h > new file mode 100644 > index 0000000000..81c9deb384 > --- /dev/null > +++ b/hw/arm/tegra241-cmdqv.h > @@ -0,0 +1,23 @@ > +/* > + * Copyright (C) 2025, NVIDIA CORPORATION > + * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3 > + * > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_TEGRA241_CMDQV_H nit: to match existing pattern this should be HW_ARM_TEGRA241_CMDQV_H > +#define HW_TEGRA241_CMDQV_H > + > +#include CONFIG_DEVICES > + > +#ifdef CONFIG_TEGRA241_CMDQV > +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); > +#else > +static inline const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void) > +{ > + return NULL; > +} > +#endif > +#endif /* HW_TEGRA241_CMDQV_H */