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Wed, 15 May 2024 07:29:01 -0700 (PDT) Message-ID: <0d9ebd11-3eae-4612-ae02-790c2f382942@ventanamicro.com> Date: Wed, 15 May 2024 11:28:56 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h To: Eric Cheng , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, tjeznach@rivosinc.com References: <20240307160319.675044-1-dbarboza@ventanamicro.com> <20240307160319.675044-3-dbarboza@ventanamicro.com> <637ee935-6753-468e-b003-e0f544d468fc@gmail.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <637ee935-6753-468e-b003-e0f544d468fc@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 5/15/24 07:02, Eric Cheng wrote: > On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: >> From: Tomasz Jeznach >> >> This header will be used by the RISC-V IOMMU emulation to be added >> in the next patch. Due to its size it's being sent in separate for >> an easier review. >> >> One thing to notice is that this header can be replaced by the future >> Linux RISC-V IOMMU driver header, which would become a linux-header we >> would import instead of keeping our own. The Linux implementation isn't >> upstream yet so for now we'll have to manage riscv-iommu-bits.h. >> >> Signed-off-by: Tomasz Jeznach >> Signed-off-by: Daniel Henrique Barboza >> --- >>   hw/riscv/riscv-iommu-bits.h | 335 ++++++++++++++++++++++++++++++++++++ >>   1 file changed, 335 insertions(+) >>   create mode 100644 hw/riscv/riscv-iommu-bits.h >> >> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h >> new file mode 100644 >> index 0000000000..8e80b1e52a >> --- /dev/null >> +++ b/hw/riscv/riscv-iommu-bits.h >> @@ -0,0 +1,335 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright © 2022-2023 Rivos Inc. >> + * Copyright © 2023 FORTH-ICS/CARV >> + * Copyright © 2023 RISC-V IOMMU Task Group >> + * >> + * RISC-V Ziommu - Register Layout and Data Structures. > > Is there still the term Ziommu today? cannot be googled. May be just a transient term during spec development? it puzzles new comers. Fair point. I'll remove any 'ziommu' references in all patches. Thanks, Daniel >> + * >> + * Based on the IOMMU spec version 1.0, 3/2023 >> + * https://github.com/riscv-non-isa/riscv-iommu >> + */ >> + > >