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X-CSE-ConnectionGUID: WNYJS9ETSHOsxg9nTMFVeA== X-CSE-MsgGUID: I6xNGYqMTt206AdXn1rUog== X-IronPort-AV: E=McAfee;i="6800,10657,11731"; a="85793274" X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="85793274" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 11:17:40 -0700 X-CSE-ConnectionGUID: fDtS/vM9SE2zpGpgmBygew== X-CSE-MsgGUID: xRLGUM+ISQ+wIh4TzWD+Kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="216482181" Received: from soc-cp83kr3.clients.intel.com (HELO [10.241.241.35]) ([10.241.241.35]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 11:17:37 -0700 Message-ID: <0e81f486-6609-4181-9b85-161c69fbb704@intel.com> Date: Mon, 16 Mar 2026 11:17:35 -0700 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 12/13] target/i386: Clean up Intel Debug Store feature dependencies To: Chenyi Qiang , qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das , Xiaoyao Li Cc: Dongli Zhang , Dapeng Mi , Hector Cao References: <20260304180713.360471-1-zide.chen@intel.com> <20260304180713.360471-13-zide.chen@intel.com> <9122d003-1e96-4790-ab32-3e06b0aa1148@intel.com> Content-Language: en-US From: "Chen, Zide" In-Reply-To: <9122d003-1e96-4790-ab32-3e06b0aa1148@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 3/15/2026 8:21 PM, Chenyi Qiang wrote: > > > On 3/5/2026 2:07 AM, Zide Chen wrote: >> - 64-bit DS Area (CPUID.01H:ECX[2]) depends on DS (CPUID.01H:EDX[21]). >> - When PMU is disabled, Debug Store must not be exposed to the guest, >> which implicitly disables legacy DS-based PEBS. >> >> Signed-off-by: Zide Chen >> --- >> V3: >> - Update title to be more accurate. >> - Make DTES64 depend on DS. >> - Mark MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL in previous patch. >> - Clean up the commit message. >> >> V2: New patch. >> --- >> target/i386/cpu.c | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index 2e1dea65d708..3ff9f76cf7da 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -1899,6 +1899,10 @@ static FeatureDep feature_dependencies[] = { >> .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, >> .to = { FEAT_PERF_CAPABILITIES, ~0ull }, >> }, >> + { >> + .from = { FEAT_1_EDX, CPUID_DTS}, >> + .to = { FEAT_1_ECX, CPUID_EXT_DTES64}, >> + }, >> { >> .from = { FEAT_1_ECX, CPUID_EXT_VMX }, >> .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, >> @@ -9471,6 +9475,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) >> env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; >> } >> >> + env->features[FEAT_1_EDX] &= ~CPUID_DTS; >> env->features[FEAT_7_0_EDX] &= ~CPUID_7_0_EDX_ARCH_LBR; > > This change, along with the original CPUID_7_0_EDX_ARCH_LBR clear, will also affect the configuration for TD VMs. > For a TD VM, enable_pmu controls TDX_TD_ATTRIBUTES_PERFMON, CPUID_DTS is fixed to 1, and arch_lbr is controlled by XFAM[15]. Yes, I agree. In the TDX case, neither the DTS nor the arch_lbr bit should be cleared. > These features' configuration do not have dependencies on each other. So how about skipping the TD VM case like: > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 98e95d0842..458bfb07b9 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -9736,8 +9736,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) > env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; > } > > - env->features[FEAT_1_EDX] &= ~CPUID_DTS; > - env->features[FEAT_7_0_EDX] &= ~CPUID_7_0_EDX_ARCH_LBR; > + if (!is_tdx_vm()) { > + env->features[FEAT_1_EDX] &= ~CPUID_DTS; > + env->features[FEAT_7_0_EDX] &= ~CPUID_7_0_EDX_ARCH_LBR; > + } > } > > for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { > > > >> } >> >