From: Tao Tang <tangtao1634@phytium.com.cn>
To: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
Eric Auger <eric.auger@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Chen Baozi" <chenbaozi@phytium.com.cn>,
"Philippe Mathieu-Daudé" <philmd@mailo.com>,
"Mostafa Saleh" <smostafa@google.com>,
"Chao Liu" <chao.liu@processmission.com>,
"Jim MacArthur" <jim.macarthur@linaro.org>
Subject: Re: [RFC v5 15/28] hw/arm/smmu: Make CMDQ invalidation security-state aware
Date: Sat, 22 Aug 2026 00:00:00 +0800 [thread overview]
Message-ID: <0f3cec2d-a184-4fdf-b4e1-d7d2ae4a67fb@phytium.com.cn> (raw)
In-Reply-To: <4b80bd7c-1002-4ae4-a9fe-7449c0637687@oss.qualcomm.com>
Hi Pierrick,
On 8/21/2026 6:29 AM, Pierrick Bouvier wrote:
> On 8/13/2026 9:25 AM, Tao Tang wrote:
>> Refactor CMDQ invalidation paths to carry security state and apply cache
>> invalidation per sec_sid instead of globally. Add separate helpers for
>> invalidating all entries and for invalidating entries belonging to one
>> valid sec_sid.
>>
>> In smmuv3, propagate the command queue sec_sid and command SSec through
>> CFGI and TLBI handling, and gate VMID use on the stage-2 capability of
>> the selected command queue, including SMMU_S_IDR1.SEL2 for a Secure
>> Command queue.
>>
>> Keep acceleration and IOMMU notifier propagation Non-secure-only.
>> Commands targeting a programming interface other than Non-secure do not
>> reach the accelerated backend or Non-secure notifiers, while Non-secure
>> stage-1 CMD_TLBI_NH_ALL remains forwarded to the host.
>>
>> Include the command queue SEC_SID and target SEC_SID in the relevant
>> invalidation tracepoints.
>>
>> Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
>> ---
>> hw/arm/smmu-common.c | 100 ++++++++++++++++++++++++++++-
>> hw/arm/smmuv3-accel-stubs.c | 6 +-
>> hw/arm/smmuv3-accel.c | 30 +++++++--
>> hw/arm/smmuv3-accel.h | 6 +-
>> hw/arm/smmuv3.c | 121 ++++++++++++++++++++++++++---------
>> hw/arm/trace-events | 12 ++--
>> include/hw/arm/smmu-common.h | 6 ++
>> 7 files changed, 231 insertions(+), 50 deletions(-)
>>
> Given this patch, would that be simpler to have multiple iotlb hashtable
> per sec_sid? This way, invalidation becomes trivial.
>
> It has been long time since last version, so I forgot if there was a
> specific reason to keep a single table and add sec_sid to each entry.
I agree that separate IOTLB tables per SEC_SID would simplify the
namespace-wide invalidation in the current model. Mostafa made the same
suggestion in v4 [1], and I agreed to rework it for v5.
As Eric later pointed out [2], SEC_SID is not itself the architectural
TLB tag. It selects the programming interface and Stream table, while
cached translations are identified by the effective StreamWorld and the
applicable ASID/VMID.
My reason for retaining the single table is therefore patch scope, not
an architectural objection to per-SEC_SID tables. This series models one
StreamWorld per SEC_SID and uses SEC_SID as a temporary discriminator,
as described in the definition of struct SMMUIOTLBKey [3]. I would
prefer to keep the cache topology unchanged here and address the layout
together with full StreamWorld tagging and invalidation in a follow-up
series.
Eric, would you prefer that v6 adopt the per-SEC_SID split suggested by
Pierrick and Mostafa, or keep the current layout and defer the topology
decision to the StreamWorld work? I am happy to follow the preferred
direction.
[1] https://lore.kernel.org/qemu-devel/aaGuGuevX8HFqx0x@google.com/
[2]
https://lore.kernel.org/qemu-devel/72026588-1db3-48a1-af99-e5e2aca69058@redhat.com/
[3]
https://lore.kernel.org/qemu-devel/20260813162512.2807281-2-tangtao1634@phytium.com.cn/
> Regards,
> Pierrick
Best regards,
Tao
next prev parent reply other threads:[~2026-08-21 16:01 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-13 16:15 [RFC v5 00/28] hw/arm/smmuv3: Support Secure state for SMMUv3 Tao Tang
2026-08-13 16:21 ` [RFC v5 23/28] hw/pci: Add sec-sid property to PCIDevice Tao Tang
2026-08-13 16:24 ` [RFC v5 01/28] hw/arm/smmuv3: Introduce secure registers Tao Tang
2026-08-18 14:21 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 02/28] hw/arm/smmuv3: Introduce banked registers for SMMUv3 state Tao Tang
2026-08-21 9:52 ` Jim MacArthur
2026-08-21 16:03 ` Tao Tang
2026-08-13 16:24 ` [RFC v5 03/28] hw/arm/smmuv3: Thread SEC_SID through helper APIs Tao Tang
2026-08-21 10:09 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 04/28] hw/arm/smmuv3: Track SEC_SID in configs and events Tao Tang
2026-08-21 12:35 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 05/28] hw/arm/smmu-common: Add security-aware address space selector Tao Tang
2026-08-20 22:17 ` Pierrick Bouvier
2026-08-13 16:24 ` [RFC v5 06/28] hw/arm/smmuv3: Plumb transaction attributes into config helpers Tao Tang
2026-08-20 22:19 ` Pierrick Bouvier
2026-08-13 16:24 ` [RFC v5 07/28] hw/arm/smmuv3: Reject secure STEs with stage-2 enabled Tao Tang
2026-08-20 22:19 ` Pierrick Bouvier
2026-08-13 16:24 ` [RFC v5 08/28] hw/arm/smmu-common: Key configuration cache on SMMUDevice and SEC_SID Tao Tang
2026-08-21 15:01 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 09/28] hw/arm/smmu: Add PTE NS/NSTable helpers Tao Tang
2026-08-21 15:14 ` Jim MacArthur
2026-08-13 16:24 ` [RFC v5 10/28] hw/arm/smmuv3: Store CD NSCFG in TT info Tao Tang
2026-08-21 15:16 ` Jim MacArthur
2026-08-13 16:25 ` [RFC v5 11/28] hw/arm/smmu-common: Implement secure state handling in ptw Tao Tang
2026-08-20 22:26 ` Pierrick Bouvier
2026-08-13 16:25 ` [RFC v5 12/28] hw/arm/smmuv3: Tag IOTLB cache keys with SEC_SID Tao Tang
2026-08-20 22:21 ` Pierrick Bouvier
2026-08-13 16:25 ` [RFC v5 13/28] hw/arm/smmuv3: Pass sec_sid into cmdq consume path Tao Tang
2026-08-21 15:57 ` Jim MacArthur
2026-08-13 16:25 ` [RFC v5 14/28] hw/arm/smmuv3: Make evtq producer use SEC_SID Tao Tang
2026-08-21 15:58 ` Jim MacArthur
2026-08-13 16:25 ` [RFC v5 15/28] hw/arm/smmu: Make CMDQ invalidation security-state aware Tao Tang
2026-08-20 22:29 ` Pierrick Bouvier
2026-08-21 16:00 ` Tao Tang [this message]
2026-08-13 16:25 ` [RFC v5 16/28] hw/arm/smmuv3: Add access checks for GERROR_IRQ_CFG registers Tao Tang
2026-08-13 16:25 ` [RFC v5 17/28] hw/arm/smmuv3: Add access checks for STRTAB_BASE and CR2 registers Tao Tang
2026-08-13 16:25 ` [RFC v5 18/28] hw/arm/smmuv3: Add access checks for CMDQ and EVENTQ registers Tao Tang
2026-08-13 16:25 ` [RFC v5 19/28] hw/arm/smmuv3: Determine register bank from MMIO offset Tao Tang
2026-08-13 16:25 ` [RFC v5 20/28] hw/arm/smmuv3: Route IRQ and GERROR handling by SEC_SID Tao Tang
2026-08-20 22:23 ` Pierrick Bouvier
2026-08-13 16:26 ` [RFC v5 21/28] hw/arm/smmuv3: Implement SMMU_S_INIT register Tao Tang
2026-08-13 16:26 ` [RFC v5 22/28] hw/arm/smmuv3: Harden security checks in MMIO handlers Tao Tang
2026-08-13 16:26 ` [RFC v5 24/28] hw/arm/smmuv3: Select sec-sid from PCI property and validate SECURE_IMPL Tao Tang
2026-08-13 16:26 ` [RFC v5 25/28] hw/arm/smmuv3: Reject IOMMU notifiers for non-NS devices Tao Tang
2026-08-20 22:23 ` Pierrick Bouvier
2026-08-13 16:26 ` [RFC v5 26/28] hw/arm/smmuv3: Initialize the secure register bank Tao Tang
2026-08-13 16:26 ` [RFC v5 27/28] hw/arm/smmuv3: Add secure bank migration and secure-impl property Tao Tang
2026-08-13 16:26 ` [RFC v5 28/28] [NOT-MERGE] hw/arm/smmuv3: temporarily enable SEL2 bit and some other features Tao Tang
2026-08-20 22:16 ` [RFC v5 00/28] hw/arm/smmuv3: Support Secure state for SMMUv3 Pierrick Bouvier
2026-08-21 16:15 ` Tao Tang
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