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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
	intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, ankit.k.nautiyal@intel.com
Subject: Re: [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable
Date: Tue, 24 Jun 2025 11:25:00 +0300	[thread overview]
Message-ID: <0f88bf4afbbe2bc08574e7fa08d1cfcb4141fac6@intel.com> (raw)
In-Reply-To: <20250624074948.671761-13-mitulkumar.ajitkumar.golani@intel.com>

On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add function to control DC balance enable/disable bit via DSB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dmc.h |  5 +++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 4572e87d9bfa..1726c0ab18c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1607,3 +1607,21 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
>  		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
>  			crtc->base.base.id, crtc->base.name, tmp);
>  }
> +
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
> +			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
> +}
> +
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum pipe pipe = crtc->pipe;
> +
> +	intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 7820fa5aed3e..d45d51bedb87 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -8,11 +8,14 @@
>  
>  #include <linux/types.h>
>  
> +

Please run checkpatch before sending.

>  enum pipe;
> +struct intel_crtc;
>  struct drm_printer;
>  struct intel_crtc_state;
>  struct intel_display;
>  struct intel_dmc_snapshot;
> +struct intel_dsb;
>  
>  void intel_dmc_init(struct intel_display *display);
>  void intel_dmc_load_program(struct intel_display *display);
> @@ -36,5 +39,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
>  void assert_main_dmc_loaded(struct intel_display *display);
>  
>  void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
>  
>  #endif /* __INTEL_DMC_H__ */

-- 
Jani Nikula, Intel

  reply	other threads:[~2025-06-24  8:25 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-24  7:49 [PATCH v7 00/18] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-06-24  7:49 ` [PATCH v7 01/18] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-06-24  7:49 ` [PATCH v7 02/18] drm/i915/display: Add source param for dc balance Mitul Golani
2025-06-24  7:49 ` [PATCH v7 03/18] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-06-24  7:49 ` [PATCH v7 04/18] drm/i915/display: Add VRR DC balance registers Mitul Golani
2025-06-24  8:13   ` Jani Nikula
2025-06-24  7:49 ` [PATCH v7 05/18] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-06-24  7:49 ` [PATCH v7 06/18] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-06-24  8:14   ` Jani Nikula
2025-06-24  7:49 ` [PATCH v7 07/18] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-06-24  7:49 ` [PATCH v7 08/18] drm/i915/vrr: Add compute config " Mitul Golani
2025-06-24  7:49 ` [PATCH v7 09/18] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-06-24  7:49 ` [PATCH v7 10/18] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-06-24  7:49 ` [PATCH v7 11/18] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-06-24  7:49 ` [PATCH v7 12/18] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-06-24  8:25   ` Jani Nikula [this message]
2025-06-24  7:49 ` [PATCH v7 13/18] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-06-24  7:49 ` [PATCH v7 14/18] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-06-24  7:49 ` [PATCH v7 15/18] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-06-24  7:49 ` [PATCH v7 16/18] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
2025-06-24  7:49 ` [PATCH v7 17/18] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-06-24  7:49 ` [PATCH v7 18/18] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-06-24  8:54 ` ✓ i915.CI.BAT: success for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
2025-06-24 10:50 ` ✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB (rev8) Patchwork
2025-06-24 10:51 ` ✓ CI.KUnit: success " Patchwork
2025-06-24 11:06 ` ✗ CI.checksparse: warning " Patchwork
2025-06-24 11:35 ` ✓ Xe.CI.BAT: success " Patchwork
2025-06-24 12:40 ` ✗ i915.CI.Full: failure for Enable/Disable DC balance along with VRR DSB (rev7) Patchwork
2025-06-24 21:23 ` ✗ Xe.CI.Full: failure for Enable/Disable DC balance along with VRR DSB (rev8) Patchwork

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