From: "Summers, Stuart" <stuart.summers@intel.com>
To: "igt-dev@lists.freedesktop.org" <igt-dev@lists.freedesktop.org>,
"Vishwanathapura,
Niranjana" <niranjana.vishwanathapura@intel.com>
Cc: "Ch, Sai Gowtham" <sai.gowtham.ch@intel.com>,
"Dandamudi, Priyanka" <priyanka.dandamudi@intel.com>,
"kamil.konieczny@linux.intel.com"
<kamil.konieczny@linux.intel.com>
Subject: Re: [PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec submissions
Date: Thu, 4 Dec 2025 20:42:38 +0000 [thread overview]
Message-ID: <0fba937668b0efa646718fa7b032dbd321c7d4e8.camel@intel.com> (raw)
In-Reply-To: <20251121035715.767226-25-niranjana.vishwanathapura@intel.com>
On Thu, 2025-11-20 at 19:57 -0800, Niranjana Vishwanathapura wrote:
> Validate multi queue feature with different queue group size
> and with execbuf submissions.
>
> v2: Use BASE_ADDRESS macro for address (Sai)
>
> Signed-off-by: Niranjana Vishwanathapura
> <niranjana.vishwanathapura@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> tests/intel/xe_exec_multi_queue.c | 199
> ++++++++++++++++++++++++++++++
> 1 file changed, 199 insertions(+)
>
> diff --git a/tests/intel/xe_exec_multi_queue.c
> b/tests/intel/xe_exec_multi_queue.c
> index 03b920dc8..977b4e7a0 100644
> --- a/tests/intel/xe_exec_multi_queue.c
> +++ b/tests/intel/xe_exec_multi_queue.c
> @@ -13,16 +13,21 @@
>
> #include "igt.h"
> #include "xe_drm.h"
> +#include "lib/igt_syncobj.h"
>
> #include "xe/xe_ioctl.h"
> #include "xe/xe_query.h"
>
> #define MAX_N_EXEC_QUEUES 64
>
> +#define USERPTR (0x1 << 0)
> +
> #define MAX_INSTANCE 9
>
> #define XE_MULTI_GROUP_VALID_FLAGS (DRM_XE_MULTI_GROUP_CREATE)
>
> +#define BASE_ADDRESS 0x1a0000
> +
> static void
> __test_sanity(int fd, int gt, int class)
> {
> @@ -144,8 +149,175 @@ test_sanity(int fd, int gt, int class)
> __test_sanity(fd, gt, class);
> }
>
> +static void
> +test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
> int num_placement,
> + int n_exec_queues, int n_execs, unsigned int flags)
> +{
> + struct drm_xe_sync sync[2] = {
> + { .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> DRM_XE_SYNC_FLAG_SIGNAL, },
> + { .flags = DRM_XE_SYNC_TYPE_SYNCOBJ |
> DRM_XE_SYNC_FLAG_SIGNAL, },
> + };
> +
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 2,
> + .syncs = to_user_pointer(sync),
> + };
> + uint32_t vm;
> + uint64_t addr = BASE_ADDRESS;
> + uint32_t exec_queues[MAX_N_EXEC_QUEUES];
> + uint32_t syncobjs[MAX_N_EXEC_QUEUES];
> + uint32_t bind_syncobj;
> + size_t bo_size;
> + uint32_t bo = 0;
> + struct {
> + uint32_t batch[16];
> + uint64_t pad;
> + uint32_t data;
> + } *data;
> + int i, b;
> +
> + igt_assert(n_exec_queues <= MAX_N_EXEC_QUEUES);
> + vm = xe_vm_create(fd, 0, 0);
> + bo_size = xe_bb_size(fd, sizeof(*data) * n_execs);
> +
> + if (flags & USERPTR) {
> + data = aligned_alloc(xe_get_default_alignment(fd),
> bo_size);
> + igt_assert(data);
> +
> + memset(data, 0, bo_size);
> + } else {
> + bo = xe_bo_create(fd, vm, bo_size,
> vram_if_possible(fd, eci[0].gt_id),
> +
> DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> + data = xe_bo_map(fd, bo, bo_size);
> + }
> +
> + for (i = 0; i < n_exec_queues; i++) {
> + struct drm_xe_ext_set_property multi_queue = {
> + .base.name =
> DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY,
> + .property =
> DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP,
> + };
> + uint64_t ext = to_user_pointer(&multi_queue);
> +
> + multi_queue.value = i ? exec_queues[0] :
> DRM_XE_MULTI_GROUP_CREATE;
> + igt_assert_eq(__xe_exec_queue_create(fd, vm, 1,
> num_placement, eci,
> + ext,
> &exec_queues[i]), 0);
> +
> + syncobjs[i] = syncobj_create(fd, 0);
> + };
> +
> + bind_syncobj = syncobj_create(fd, 0);
> + sync[0].handle = bind_syncobj;
> + if (bo)
> + xe_vm_bind_async(fd, vm, 0, bo, 0, addr, bo_size,
> sync, 1);
> + else
> + xe_vm_bind_userptr_async(fd, vm, 0,
> to_user_pointer(data),
> + addr, bo_size, sync, 1);
> +
> + for (i = 0; i < n_execs; i++) {
> + uint64_t batch_offset = (char *)&data[i].batch -
> (char *)data;
> + uint64_t batch_addr = addr + batch_offset;
> + uint64_t sdi_offset = (char *)&data[i].data - (char
> *)data;
> + uint64_t sdi_addr = addr + sdi_offset;
> + int e = i % n_exec_queues;
> +
> + b = 0;
> + data[i].batch[b++] = MI_STORE_DWORD_IMM_GEN4;
> + data[i].batch[b++] = sdi_addr;
> + data[i].batch[b++] = sdi_addr >> 32;
> + data[i].batch[b++] = 0xc0ffee;
> + data[i].batch[b++] = MI_BATCH_BUFFER_END;
> + igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> + sync[0].flags &= ~DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[0].handle = bind_syncobj;
> + sync[1].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + sync[1].handle = syncobjs[e];
> +
> + exec.exec_queue_id = exec_queues[e];
> + exec.address = batch_addr;
> + if (e != i)
> + syncobj_reset(fd, &syncobjs[e], 1);
> +
> + xe_exec(fd, &exec);
> + }
> +
> + for (i = 0; i < n_exec_queues && i < n_execs; i++)
> + igt_assert(syncobj_wait(fd, &syncobjs[i], 1,
> INT64_MAX, 0, NULL));
> +
> + igt_assert(syncobj_wait(fd, &bind_syncobj, 1, INT64_MAX, 0,
> NULL));
> + sync[0].flags |= DRM_XE_SYNC_FLAG_SIGNAL;
> + syncobj_reset(fd, &sync[0].handle, 1);
> + xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
> + igt_assert(syncobj_wait(fd, &sync[0].handle, 1, INT64_MAX, 0,
> NULL));
> +
> + for (i = 0; i < n_execs; i++)
> + igt_assert_eq(data[i].data, 0xc0ffee);
> +
> + for (i = 0; i < n_exec_queues; i++) {
> + syncobj_destroy(fd, syncobjs[i]);
> + xe_exec_queue_destroy(fd, exec_queues[i]);
> + }
> +
> + if (bo) {
> + munmap(data, bo_size);
> + gem_close(fd, bo);
> + } else {
> + free(data);
> + }
> +
> + syncobj_destroy(fd, bind_syncobj);
> + xe_vm_destroy(fd, vm);
> +}
> +
> +/**
> + * SUBTEST: one-queue-%s
> + * Description: Run %arg[1] test with one exec queue
> + * Test category: functionality test
> + *
> + * SUBTEST: two-queues-%s
> + * Description: Run %arg[1] test with two exec queues
> + * Test category: functionality test
> + *
> + * SUBTEST: many-queues-%s
> + * Description: Run %arg[1] test with many exec queues
> + * Test category: stress test
> + *
> + * SUBTEST: max-queues-%s
> + * Description: Run %arg[1] test with max exec queues
> + * Test category: stress test
> + *
> + * SUBTEST: many-execs-%s
> + * Description: Run %arg[1] test with many exec submissions per exec
> queue
> + * Test category: functionality test
> + *
> + * SUBTEST: few-execs-%s
> + * Description: Run %arg[1] test with exec submissions only on few
> exec queues
> + * Test category: functionality test
> + *
> + * arg[1]:
> + *
> + * @basic: basic
> + * @userptr: userptr
> + */
> +static void
> +test_exec(int fd, struct drm_xe_engine_class_instance *eci, int
> num_placement,
> + int n_exec_queues, int n_execs, unsigned int flags)
> +{
> + test_legacy_mode(fd, eci, num_placement, n_exec_queues,
> n_execs, flags);
> +}
> +
> igt_main
> {
> + struct drm_xe_engine_class_instance *hwe;
> + const struct section {
> + const char *name;
> + unsigned int flags;
> + } sections[] = {
> + { "basic", 0 },
> + { "userptr", USERPTR },
> + { NULL },
> + };
> int fd, gt, class;
>
> igt_fixture {
> @@ -158,6 +330,33 @@ igt_main
> xe_for_each_multi_queue_engine_class(class)
> test_sanity(fd, gt, class);
>
> + for (const struct section *s = sections; s->name; s++) {
> + igt_subtest_f("one-queue-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1, 1, 1, s-
> >flags);
> +
> + igt_subtest_f("two-queues-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1, 2, 2, s-
> >flags);
> +
> + igt_subtest_f("many-queues-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1, 16, 16, s-
> >flags);
> +
> + igt_subtest_f("max-queues-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1,
> MAX_N_EXEC_QUEUES,
> + MAX_N_EXEC_QUEUES, s-
> >flags);
> +
> + igt_subtest_f("many-execs-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1, 16, 64, s-
> >flags);
> +
> + igt_subtest_f("few-execs-%s", s->name)
> + xe_for_each_multi_queue_engine(fd, hwe)
> + test_exec(fd, hwe, 1, 16, 8, s-
> >flags);
> + }
> +
> igt_fixture
> drm_close_driver(fd);
> }
next prev parent reply other threads:[~2025-12-04 20:42 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-21 3:57 [PATCH v2 00/19] Multi Queue feature validation support Niranjana Vishwanathapura
2025-11-21 3:57 ` [PATCH v2 01/19] drm-uapi/xe: Sync with Multi-Queue uapi Niranjana Vishwanathapura
2025-12-04 19:19 ` Summers, Stuart
2025-12-04 20:58 ` Niranjana Vishwanathapura
2025-12-05 18:07 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 02/19] lib/xe: Add multi-queue helper routines Niranjana Vishwanathapura
2025-12-04 19:20 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 03/19] tests/intel/xe_exec_multi_queue: Add xe_exec_multi_queue test Niranjana Vishwanathapura
2025-12-04 20:02 ` Summers, Stuart
2025-12-05 1:34 ` Niranjana Vishwanathapura
2025-12-05 18:09 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 04/19] tests/intel/xe_exec_multi_queue: Validate exec submissions Niranjana Vishwanathapura
2025-12-02 5:27 ` Ch, Sai Gowtham
2025-12-04 20:42 ` Summers, Stuart [this message]
2025-11-21 3:57 ` [PATCH v2 05/19] tests/intel/xe_exec_multi_queue: Validate queue priority setting Niranjana Vishwanathapura
2025-12-02 5:29 ` Dandamudi, Priyanka
2025-12-04 20:45 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 06/19] tests/intel/xe_exec_multi_queue: Add close-fd tests Niranjana Vishwanathapura
2025-11-24 8:18 ` Goyal, Nakshtra
2025-12-04 20:46 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 07/19] tests/intel/xe_exec_multi_queue: Add multiple placement test Niranjana Vishwanathapura
2025-12-02 5:32 ` Dandamudi, Priyanka
2025-12-05 18:10 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 08/19] tests/intel/xe_exec_multi_queue: Add preempt mode test Niranjana Vishwanathapura
2025-12-04 20:52 ` Summers, Stuart
2025-12-05 19:12 ` Niranjana Vishwanathapura
2025-12-08 19:40 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 09/19] lib/xe: Add exec_queue set_property ioctl support Niranjana Vishwanathapura
2025-12-04 19:24 ` Summers, Stuart
2025-12-05 1:58 ` Niranjana Vishwanathapura
2025-12-05 18:11 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 10/19] tests/intel/xe_exec_multi_queue: Add dynamic priority test Niranjana Vishwanathapura
2025-12-04 20:53 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 11/19] tests/intel/xe_exec_multi_queue: Add userptr invalidation tests Niranjana Vishwanathapura
2025-12-04 20:56 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 12/19] tests/intel/xe_exec_multi_queue: Add fault mode test Niranjana Vishwanathapura
2025-11-21 5:04 ` Goyal, Nakshtra
2025-12-04 20:59 ` Summers, Stuart
2025-12-04 23:25 ` Niranjana Vishwanathapura
2025-12-05 18:13 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 13/19] tests/intel/xe_exec_multi_queue: Add multi queues with SMEM Niranjana Vishwanathapura
2025-12-04 19:56 ` Goyal, Nakshtra
2025-12-04 20:59 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 14/19] lib/xe/xe_spin: Add switch point for preemptible spinner Niranjana Vishwanathapura
2025-12-04 21:03 ` Summers, Stuart
2025-12-04 21:42 ` Niranjana Vishwanathapura
2025-12-05 18:45 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 15/19] tests/intel/xe_exec_multi_queue: Add priority test Niranjana Vishwanathapura
2025-12-02 5:28 ` Dandamudi, Priyanka
2025-12-04 21:53 ` Summers, Stuart
2025-12-05 18:23 ` Niranjana Vishwanathapura
2025-12-08 19:38 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 16/19] tests/intel/xe_exec_multi_queue: Add submission sanity test Niranjana Vishwanathapura
2025-12-02 11:46 ` Ch, Sai Gowtham
2025-12-04 21:08 ` Summers, Stuart
2025-12-04 21:28 ` Niranjana Vishwanathapura
2025-11-21 3:57 ` [PATCH v2 17/19] tests/intel/xe_exec_multi_queue: Sanity test KEEP_ACTIVE flag Niranjana Vishwanathapura
2025-12-04 21:10 ` Summers, Stuart
2025-12-04 21:20 ` Niranjana Vishwanathapura
2025-11-21 3:57 ` [PATCH v2 18/19] tests/intel/xe_exec_multi_queue: Keep group active in exec-sanity Niranjana Vishwanathapura
2025-12-02 11:51 ` Ch, Sai Gowtham
2025-12-04 21:12 ` Summers, Stuart
2025-11-21 3:57 ` [PATCH v2 19/19] tests/intel/xe_exec_queue_property: Update invalid-property test Niranjana Vishwanathapura
2025-12-04 19:25 ` Summers, Stuart
2025-12-04 21:11 ` Niranjana Vishwanathapura
2025-11-21 4:32 ` ✓ Xe.CI.BAT: success for Multi Queue feature validation support (rev2) Patchwork
2025-11-21 6:47 ` ✓ i915.CI.BAT: " Patchwork
2025-11-21 7:20 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-21 9:42 ` ✗ i915.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0fba937668b0efa646718fa7b032dbd321c7d4e8.camel@intel.com \
--to=stuart.summers@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=kamil.konieczny@linux.intel.com \
--cc=niranjana.vishwanathapura@intel.com \
--cc=priyanka.dandamudi@intel.com \
--cc=sai.gowtham.ch@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.