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([2a01:e0a:c:37e0:ced3:55bd:f454:e722]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43890461fc6sm136098005e9.29.2025.01.20.02.37.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jan 2025 02:37:18 -0800 (PST) Message-ID: <0fc51a94-fdf1-43cf-82aa-d0b0a673f1ca@redhat.com> Date: Mon, 20 Jan 2025 11:37:17 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch To: Thomas Zimmermann , airlied@redhat.com Cc: dri-devel@lists.freedesktop.org References: <20250117103450.28692-1-tzimmermann@suse.de> <20250117103450.28692-6-tzimmermann@suse.de> From: Jocelyn Falempe In-Reply-To: <20250117103450.28692-6-tzimmermann@suse.de> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: orVE0j9sXcq6kioPUNPvkfHudsLwyBPPOKYgO5t496Y_1737369439 X-Mimecast-Originator: redhat.com Content-Language: en-US, fr Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 17/01/2025 11:29, Thomas Zimmermann wrote: > Gen7 only supports ASTDP. Gens 4 to 6 support various TX chips, > except ASTDP. These boards detect the TX chips by reading the SoC > scratch register as VGACRD1. > > Gens 1 to 3 only support SIL164. These boards read the DVO bit from > VGACRA3. Hence move this test behind a branch, so that it does not > run on later generations. Thanks, it looks good to me. Reviewed-by: Jocelyn Falempe > > Signed-off-by: Thomas Zimmermann > --- > drivers/gpu/drm/ast/ast_main.c | 30 +++++++++++++++--------------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index 474eb255b325b..50b57bc15d53c 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -96,21 +96,21 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post) > /* Check 3rd Tx option (digital output afaik) */ > ast->tx_chip = AST_TX_NONE; > > - /* > - * VGACRA3 Enhanced Color Mode Register, check if DVO is already > - * enabled, in that case, assume we have a SIL164 TMDS transmitter > - * > - * Don't make that assumption if we the chip wasn't enabled and > - * is at power-on reset, otherwise we'll incorrectly "detect" a > - * SIL164 when there is none. > - */ > - if (!need_post) { > - jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); > - if (jreg & 0x80) > - ast->tx_chip = AST_TX_SIL164; > - } > - > - if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) { > + if (AST_GEN(ast) <= 3) { > + /* > + * VGACRA3 Enhanced Color Mode Register, check if DVO is already > + * enabled, in that case, assume we have a SIL164 TMDS transmitter > + * > + * Don't make that assumption if we the chip wasn't enabled and > + * is at power-on reset, otherwise we'll incorrectly "detect" a > + * SIL164 when there is none. > + */ > + if (!need_post) { > + jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); > + if (jreg & 0x80) > + ast->tx_chip = AST_TX_SIL164; > + } > + } else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) { > /* > * On AST GEN4+, look the configuration set by the SoC in > * the SOC scratch register #1 bits 11:8 (interestingly marked