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[84.0.18.144]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49230a4601esm61009175e9.1.2026.06.16.04.54.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 04:54:20 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, Natalie Vock , Mario Limonciello , Amir Shetaia , Marek =?UTF-8?B?T2zFocOhaw==?= , Tvrtko Ursulin Subject: Re: [PATCH 5/7] drm/amdgpu/gfxhub: Enable retry fault interrupts when needed Date: Tue, 16 Jun 2026 13:54:20 +0200 Message-ID: <10181145.eNJFYEL58v@timur-hyperion> In-Reply-To: References: <20260525114507.24566-1-timur.kristof@gmail.com> <20260525114507.24566-6-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tuesday, June 16, 2026 10:02:44=E2=80=AFAM Central European Summer Time = Tvrtko=20 Ursulin wrote: > On 25/05/2026 12:45, Timur Krist=C3=B3f wrote: > > Enable retry fault interrupts when initializing the GFXHUB > > system aperture registers according to whether retrying > > page faults is enabled in amdgpu (ie. amdgpu.noretry=3D0). > >=20 > > Needs to be done for each GFXHUB version at once, > > because none of them actually enabled this interrupt. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 2 ++ > > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 9 +++++++-- > > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 9 +++++++-- > > 8 files changed, 51 insertions(+), 14 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c index > > 652eea6eae4a..ef20eafd59ae 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > > @@ -155,6 +155,7 @@ static void > > gfxhub_v11_5_0_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v11_5_0_init_system_aperture_regs(struct > > amdgpu_device *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >>=20 24); > >=20 > > @@ -180,8 +181,12 @@ static void > > gfxhub_v11_5_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); >=20 > As a side note, I have two patches which shrink these register access > macros considerably: >=20 > https://patchwork.freedesktop.org/patch/720726/?series=3D165432&rev=3D1 >=20 > Going back to this patch, a question - how do gfxhub ip versions relate > to the default set from gc ip versions in amdgpu_gmc_noretry_set()? I am > wondering on which platforms, if any, do at this point in the series, > retry fault interrupts get enabled where they previously were not. As far as I know, currently retry faults are only enabled by default on som= e=20 datacenter GPUs and not for any consumer GPUs. This patch just makes sure to actually program the registers to enable retr= y=20 faults when they need to be enabled (at the moment, this means, when the us= er=20 has amdgpu.noretry=3D0 on their kernel command line). The series does not c= hange=20 which generations have it enabled by default. In order to enable retry faults by default, I would like to make work relia= bly=20 first. At the moment that blocked by Christian's recent refactor which is=20 currently under review. I will have to rebase those two patches once=20 Christian's work lands. Then we can consider enabling retry faults by defau= lt=20 on Navi 3 and Navi 4 dGPUs. Note that APUs and Navi 1-2 dGPUs will still need more work because they do= n't=20 have the retry CAM so they will need a better way to filter the page fault= =20 interrupts. However I don't want to start working on that until the current= =20 three series is reviewed. Thanks, Timur >=20 > > } > > =20 > > static void gfxhub_v11_5_0_init_tlb_regs(struct amdgpu_device *adev) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c index > > 6cbf837d50dd..ec3ff4dec674 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c > > @@ -158,6 +158,7 @@ static void > > gfxhub_v12_0_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_devi= ce > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > /* Program the AGP BAR */ > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > >=20 > > @@ -184,8 +185,12 @@ static void > > gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index > > bfe247b1a333..27d7f7cb903f 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > > @@ -91,6 +91,7 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct > > amdgpu_device *adev)>=20 > > static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (!amdgpu_sriov_vf(adev) || adev->asic_type <=3D CHIP_VEGA10) { > > =09 > > /* Program the AGP BAR */ > >=20 > > @@ -134,8 +135,12 @@ static void > > gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >>=20 44)); > >=20 > > - WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,=20 1); > > + tmp =3D RREG32_SOC15(GC, 0,=20 mmVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ENABLE_RETRY_FAULT_INTERRUPT, !adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2,=20 tmp); > >=20 > > } > > =09 > > /* In the case squeezing vram into GART aperture, we don't use > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c index > > fbdf46070b38..ed9a64bc5aaa 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > > @@ -176,6 +176,8 @@ gfxhub_v1_2_xcc_init_system_aperture_regs(struct > > amdgpu_device *adev,>=20 > > tmp =3D RREG32_SOC15(GC, GET_INST(GC, i), > > regVM_L2_PROTECTION_FAULT_CNTL2); > > tmp =3D REG_SET_FIELD(tmp,=20 VM_L2_PROTECTION_FAULT_CNTL2, > > =09 > > =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > >=20 > > + tmp =3D REG_SET_FIELD(tmp,=20 VM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ENABLE_RETRY_FAULT_INTERRUPT, !adev->gmc.noretry); > >=20 > > WREG32_SOC15(GC, GET_INST(GC, i),=20 regVM_L2_PROTECTION_FAULT_CNTL2, > > tmp); > > =09 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c index > > 9ea593e2c719..152b2735d360 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > > @@ -151,6 +151,7 @@ static void gfxhub_v2_0_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (!amdgpu_sriov_vf(adev)) { > > =09 > > /* Program the AGP BAR */ > >=20 > > @@ -178,8 +179,12 @@ static void > > gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c index > > 30b90d35abd0..83c2ddbbd292 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > > @@ -154,6 +154,7 @@ static void gfxhub_v2_1_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (amdgpu_sriov_vf(adev)) > > =09 > > return; > >=20 > > @@ -182,8 +183,12 @@ static void > > gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c index > > 9e6a6e13dec0..90bbb2fe4884 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > > @@ -150,6 +150,7 @@ static void gfxhub_v3_0_init_gart_aperture_regs(str= uct > > amdgpu_device *adev)>=20 > > static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > /* Program the AGP BAR */ > > WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); > >=20 > > @@ -176,8 +177,12 @@ static void > > gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > } > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c index > > b3b1085c7cd3..1b3c067ab48c 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > > @@ -153,6 +153,7 @@ static void > > gfxhub_v3_0_3_init_gart_aperture_regs(struct amdgpu_device *adev)>=20 > > static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_dev= ice > > *adev) { > > =20 > > uint64_t value; > >=20 > > + u32 tmp; > >=20 > > if (amdgpu_sriov_vf(adev)) > > =09 > > return; > >=20 > > @@ -181,8 +182,12 @@ static void > > gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)>=20 > > WREG32_SOC15(GC, 0,=20 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, > > =09 > > (u32)((u64)adev->dummy_page_addr >> 44)); > >=20 > > - WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, > > - ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + =20 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); > > + tmp =3D REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, > > + ENABLE_RETRY_FAULT_INTERRUPT, ! adev->gmc.noretry); > > + WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); > >=20 > > }