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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ULa+YXtSLjjVHdF2t/s72OhP2AT9yAAX/yZ42zNoGpa2R/Jx929U1/p1FMoz?= =?us-ascii?Q?Dw0RuFkmvf79eYm+GtjIaBagLaG3MXgycWmbSY1VjvpM+HAjPpboFZu7ik5D?= =?us-ascii?Q?hZg7mzLu3tJIYpb0Fn0RO4S8HczDdeFt6mjM2id2hyZHQBTJOqpRKbO1tKn+?= =?us-ascii?Q?ZjTVoOVwQfL/yeK5oAH6rCVf9hYGjAM+VRVux8XiZ82po0askgAU5FufJI4Y?= =?us-ascii?Q?3ide9PWslcCeEx8tqEOOm1SIZXU1YF1OJ58B5qq9qpoDnr6DG4PWtSa32pUp?= =?us-ascii?Q?IsaaiHes95PdV4satO1HwvJnKk7o8xjTBMfaXK3M9Ust0+D5a0M59w5rTmW3?= =?us-ascii?Q?GHfYx0VMhmXALPfHif9NiJqmzpW/5rqwcMoYcWQMOsiFSY3OGKk2LgZDtUce?= =?us-ascii?Q?fIZyCdaBHXmfKgLcBIQDznT3ZIa8Y682VMmJwr8Tiget3MUhe/Dd6nTntaBf?= =?us-ascii?Q?WMonm97Zupiyv8ZmJr/I2MpSoGk2aH48z1hZXE7heZZ59FcgZffsWVGdbWKp?= =?us-ascii?Q?vg/g8RQgcFhG1SKzgvcEWJSAAsTzjCz+SF5Q/QaneKrq7XubVnjIaX1wC88n?= =?us-ascii?Q?dxq2BqFQTF+kO79xiYQZiZmdwRwo36moa0jT3yBWoaYauES6Hfj+nt6P4R44?= =?us-ascii?Q?xOnGtvYTzT6jyxcB/a+O5XSf8hWHa5a9Z8mWQR09uhM5K7sQIFILC/91l9rV?= =?us-ascii?Q?D4zEvEFc1wPpIWQyaJdqMoPUq3TovBVXArkt0qPPD4+5PAY4RQrYFhSui5sj?= =?us-ascii?Q?HYHTQUbNqTN3JaTf+YdGN9t62vdzoDrEuAT0HjXM+EtB4HIWX8sPPj402gZb?= =?us-ascii?Q?M7nImHueaQTVaV+3G9w+pU4UAwrUBpnVLzFlUToQEmJaOjEKjD0kioLKWXeO?= =?us-ascii?Q?sgoG8YGMzcT3NehIbo/L9WRtc8SV8qVFWR5lF63s08Y1erG8IFz5HzMiB9tI?= =?us-ascii?Q?SJ0t7a7HFF7Uzpm5ZWXad2/TZ4cldpcDz+PgfdyVwTjcEq6NJ3hR5pHaKbNQ?= =?us-ascii?Q?m72tJFOB6WV5ZYlmVkoCkXlL8i9fSRFvRE8Vq6C7LukEkIi+ynsanludbc8U?= =?us-ascii?Q?4kLpSN5ScuOX7JQCo7ud1/v8x6XljNDBqmzRI+RdBptT4bYTdecjK1D7tZkS?= =?us-ascii?Q?er10njEx25fz4J0AESkfeIAqE4v/u0AMkGDPgTmTk3MikWElg2Hd6DOSO6TN?= =?us-ascii?Q?7DEkV2taBrPnuyAxlwRcBNOnfSH+e/6mo+g6Nwmlk3jsPZlXpOTXn5VMJCPr?= =?us-ascii?Q?a0Qr1sydBHDeuB4/fzrB0x+stLjjmHrVSGFnxDTQx7QmKoqOovq171tPngCB?= =?us-ascii?Q?SLiMgmXK5fe5ML1Ot96yOJEz+eu5PEhsEr8+OG0MEYygGezGqlqw6xzhWl54?= =?us-ascii?Q?+Vn6JSLCSyfpq+3U/0xuwt/TgcYN2/6HHgeFMmLTcoaZoJYoXL8/Y9wieS6p?= =?us-ascii?Q?SaS3H6LsVsq2DzODQojDudM+HUCnoGIXRhbwnutWM3Esi4ZNT4ILixFKCgQ7?= =?us-ascii?Q?YNLdA94WgMYCll6m9SMzMLBBoTnNRHUKM6/0I9Rwv1IkYrUhqidU8SRWpQMV?= =?us-ascii?Q?hafF3Phixdp/AfAx0j7g1qXq5wQmiIxC4yEVC6IJKtCWhCsdyAFtfiO3YusU?= =?us-ascii?Q?eb9WDe90H9L5GdLc/+1PRhY=3D?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 898c0395-c262-4fcb-cf00-08d9efbc7668 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 13:18:17.0668 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rfKLuumB0DbcM6l1ytN6arRpLuI4CXnkKUt3f/1v1J9S43xCALqZeFUwEwV0AQ93FduFA7/vicLlqB2LGLgoAg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR04MB9197 On 14.02.2022 14:11, Jane Malalane wrote: > On 11/02/2022 11:46, Jan Beulich wrote: >> [CAUTION - EXTERNAL EMAIL] DO NOT reply, click links, or open attachment= s unless you have verified the sender and know the content is safe. >> >> On 11.02.2022 12:29, Roger Pau Monn=C3=A9 wrote: >>> On Fri, Feb 11, 2022 at 10:06:48AM +0000, Jane Malalane wrote: >>>> On 10/02/2022 10:03, Roger Pau Monn=C3=A9 wrote: >>>>> On Mon, Feb 07, 2022 at 06:21:00PM +0000, Jane Malalane wrote: >>>>>> diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs= .c >>>>>> index 7ab15e07a0..4060aef1bd 100644 >>>>>> --- a/xen/arch/x86/hvm/vmx/vmcs.c >>>>>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c >>>>>> @@ -343,6 +343,15 @@ static int vmx_init_vmcs_config(bool bsp) >>>>>> MSR_IA32_VMX_PROCBASED_CTLS2, &mismatch); >>>>>> } >>>>>> =20 >>>>>> + /* Check whether hardware supports accelerated xapic and x2apic= . */ >>>>>> + if ( bsp ) >>>>>> + { >>>>>> + assisted_xapic_available =3D cpu_has_vmx_virtualize_apic_ac= cesses; >>>>>> + assisted_x2apic_available =3D (cpu_has_vmx_apic_reg_virt || >>>>>> + cpu_has_vmx_virtual_intr_deliv= ery) && >>>>>> + cpu_has_vmx_virtualize_x2apic_m= ode; >>>>> >>>>> I've been think about this, and it seems kind of asymmetric that for >>>>> xAPIC mode we report hw assisted support only with >>>>> virtualize_apic_accesses available, while for x2APIC we require >>>>> virtualize_x2apic_mode plus either apic_reg_virt or >>>>> virtual_intr_delivery. >>>>> >>>>> I think we likely need to be more consistent here, and report hw >>>>> assisted x2APIC support as long as virtualize_x2apic_mode is >>>>> available. >>>>> >>>>> This will likely have some effect on patch 2 also, as you will have t= o >>>>> adjust vmx_vlapic_msr_changed. >>>>> >>>>> Thanks, Roger. >>>> >>>> Any other thoughts on this? As on one hand it is asymmetric but also >>>> there isn't much assistance with only virtualize_x2apic_mode set as, i= n >>>> this case, a VM exit will be avoided only when trying to access the TP= R >>>> register. >>> >>> I've been thinking about this, and reporting hardware assisted >>> x{2}APIC virtualization with just >>> SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES or >>> SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE doesn't seem very helpful. While >>> those provide some assistance to the VMM in order to handle APIC >>> accesses, it will still require a trap into the hypervisor to handle >>> most of the accesses. >>> >>> So maybe we should only report hardware assisted support when the >>> mentioned features are present together with >>> SECONDARY_EXEC_APIC_REGISTER_VIRT? >> >> Not sure - "some assistance" seems still a little better than none at al= l. >> Which route to go depends on what exactly we intend the bit to be used f= or. >> > True. I intended this bit to be specifically for enabling=20 > assisted_x{2}apic. So, would it be inconsistent to report hardware=20 > assistance with just VIRTUALIZE_APIC_ACCESSES or VIRTUALIZE_X2APIC_MODE=20 > but still claim that x{2}apic is virtualized if no MSR accesses are=20 > intercepted with XEN_HVM_CPUID_X2APIC_VIRT (in traps.c) so that, as you=20 > say, the guest gets at least "some assistance" instead of none but we=20 > still claim x{2}apic virtualization when it is actually complete? Maybe=20 > I could also add a comment alluding to this in the xl documentation. To rephrase my earlier point: Which kind of decisions are the consumer(s) of us reporting hardware assistance going to take? In how far is there a risk that "some assistance" is overall going to lead to a loss of performance? I guess I'd need to see comment and actual code all in one place ... Jan