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From: rvk <rvkisley@yahoo.com>
To: linuxppc-embedded@ozlabs.org
Subject: Re: ML403 and PPC4xx_DMA ?
Date: Thu, 26 Apr 2007 12:51:30 -0700 (PDT)	[thread overview]
Message-ID: <10207511.post@talk.nabble.com> (raw)
In-Reply-To: <1177603586.5532.20.camel@localhost>


The core itself for 405 will not have DCR: Device control registers - becau=
se
no device control bus. Have to look at board spec for whether there is a
replacement and what that is. Based on other comments you are on uncertain
ground, likely defining a few things yourself. Interesting that the base
header has a dep for DCRN based on that config.  I assume you have UG011 do=
c
from the Xilinx website.=20

Joachim F=C3=B6rster wrote:
>=20
> Hi all,
>=20
> PS: I tried to compile a kernel image with CONFIG_PPC4xx_DMA enabled,
> but gcc complains about missing definitions in ppc4xx_dma.c ... e.g.
> DCRN_DMASR (defined in ibm405.h). Well I guess I have to have
> DCRN_MASR_BASE defined in xparameters_ml403.h .... but defined to what?
>=20
>=20
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>=20
>=20

--=20
View this message in context: http://www.nabble.com/ML403-and-PPC4xx_DMA---=
tf3652591.html#a10207511
Sent from the linuxppc-embedded mailing list archive at Nabble.com.

  reply	other threads:[~2007-04-26 19:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-04-26 16:06 ML403 and PPC4xx_DMA ? Joachim Förster
2007-04-26 19:51 ` rvk [this message]
2007-04-26 21:36 ` Rick Moleres

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