From: Adrian Cox <adrian@humboldt.co.uk>
To: "Mark A. Greer" <mgreer@mvista.com>
Cc: Tom Rini <trini@kernel.crashing.org>,
linuxppc-embedded@lists.linuxppc.org
Subject: Re: Caching in the MPC107
Date: 10 Sep 2002 18:17:43 +0100 [thread overview]
Message-ID: <1031678263.2685.64.camel@newt> (raw)
In-Reply-To: <3D7E25F4.4CC00BF8@mvista.com>
On Tue, 2002-09-10 at 18:03, Mark A. Greer wrote:
> I think I understand what you're saying. The biggest question that comes to
> my mind, though, is whether this is a problem on many of the other
> hostbridges? Most of the newer bridges will buffer a cacheline or two. Is
> this a wider issue than just the 107?
I haven't looked this closely at any other bridges. Many bridges have
buffers to prefetch data during a PCI burst read, but empty the buffers
when the PCI transaction ends. The clever feature of the MPC107 is that
it holds the data to satisfy a later read, and it snoops the 60x bus for
cycles that affect its cache.
- Adrian
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-09-10 17:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-09-09 14:23 Caching in the MPC107 Adrian Cox
2002-09-10 14:58 ` Tom Rini
2002-09-10 15:45 ` Adrian Cox
2002-09-10 17:03 ` Mark A. Greer
2002-09-10 17:17 ` Adrian Cox [this message]
2002-09-10 23:33 ` Paul Mackerras
2002-09-11 12:52 ` Adrian Cox
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