From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Antonino Daplas <adaplas@pol.net>
Cc: Sven Luther <luther@dpt-info.u-strasbg.fr>,
DRI Devel <dri-devel@lists.sourceforge.net>,
Linux Fbdev development list
<linux-fbdev-devel@lists.sourceforge.net>
Subject: Re: [Dri-devel] Re: [adaplas@pol.net: Re: Fwd: Re: [Dri-devel] future of DRI?]
Date: 03 Mar 2003 01:25:01 +0000 [thread overview]
Message-ID: <1046654701.4431.3.camel@irongate.swansea.linux.org.uk> (raw)
In-Reply-To: <1046649716.1261.20.camel@localhost.localdomain>
On Mon, 2003-03-03 at 00:01, Antonino Daplas wrote:
> > For some cases. The truth is a bit more horrible, and current fbdev has
> > the same problem here. Any early Athlon, and almost any PII/PIII derived
> > chip allows the user to bring the box down if they have access to
> > a mix of cached and uncached RAM.
> >
>
> I do not understand. Do you mean such as writing to framebuffer memory
> and making it execute?
On early athlon you prefetch non cached memory and the cpu corrupts its
cache, on PII, PII mmap frame buffer against a cached page, but the
right kind of instruction in a loop with the instruction bridging the
two memory types and run it in a tight loop
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next prev parent reply other threads:[~2003-03-03 1:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-02 21:57 [adaplas@pol.net: Re: Fwd: Re: [Dri-devel] future of DRI?] Sven Luther
2003-03-03 0:27 ` Alan Cox
2003-03-03 0:01 ` Antonino Daplas
2003-03-03 1:25 ` Alan Cox [this message]
2003-03-03 21:32 ` [Dri-devel] " Antonino Daplas
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