From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Schwarz,Andre" Subject: How to register GPIOs over PCI Date: Wed, 15 Sep 2010 21:37:31 +0200 (CEST) Message-ID: <1054265387.16.1284579451319.JavaMail.open-xchange@proteus> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0434478395168710802==" Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Grant Likely , Anton Vorontsov Cc: "devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" List-Id: devicetree@vger.kernel.org --===============0434478395168710802== Content-Type: multipart/alternative; boundary="----=_Part_15_1749540210.1284579451274" ------=_Part_15_1749540210.1284579451274 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Grant, Anton, reading through the of/gpio docs and thinking about some improvements for o= ur proprietary "ancient" code gives a lot of opportunities for major improveme= nts ... since you are authors and your quick help in the past is really appreci= ated I dare to address you directly ;-) On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI FPGA. There's no NAND controller inside ... just bitbang. Currently there's an implementation using "struct nand_chip" + hooks + nand_scan() inside the pc= i driver. Since the driver is designed to do other things and is not availabl= e during boot (=3Dno RFS on Nand) I definitely want to get rid of this. To me it looks like we could use the "gpio-nand" driver. All we need is registering the proper (mem mapped) GPIOs with the required names via device-tree. As far as I understand the FPGA can be considered an of_mm_gpio_chip ? Honestly I don't know how to define it using dts syntax. All we have regarding PCI is general bus ranges, devsel and irq lines ... a= nd of course the offset inside the FPGA. I've not seen a direct representation of a PCI device - only SoC components= . How am I supposed to handle the unknown (=3Ddynamically assigned) base addr= ess ? Since the system also has PCI slots I can't make sure to always get the sam= e adress ... Can you give some hints/advice how to define the FPGA as a GPIO-Controller = ? Regards, Andr=C3=A9 =0AMATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler=0ARegistergerich= t: Amtsgericht Stuttgart, HRB 271090=0AGeschaeftsfuehrer: Gerhard Thullner, = Werner Armingeon, Uwe Furtner=0A ------=_Part_15_1749540210.1284579451274 MIME-Version: 1.0 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit Grant, Anton,

reading through the of/gpio docs and thinking about some improvements for our proprietary "ancient" code gives a lot of opportunities for major improvements ... since you are authors and your quick help in the past is really appreciated I dare to address you directly ;-)

On some (mostly PowerPC) based boards we have NAND-Flash connected to a PCI FPGA.
There's no NAND controller inside ... just bitbang. Currently there's an implementation using "struct nand_chip" + hooks + nand_scan() inside the pci driver. Since the driver is designed to do other things and is not available during boot (=no RFS on Nand) I definitely want to get rid of this.

To me it looks like we could use the "gpio-nand" driver. All we need is registering the proper (mem mapped) GPIOs with the required names via device-tree. As far as I understand the FPGA can be considered an of_mm_gpio_chip ?

Honestly I don't know how to define it using dts syntax.

All we have regarding PCI is general bus ranges, devsel and irq lines ... and of course the offset inside the FPGA.
I've not seen a direct representation of a PCI device - only SoC components.

How am I supposed to handle the unknown (=dynamically assigned) base address ?
Since the system also has PCI slots I can't make sure to always get the same adress ...


Can you give some hints/advice how to define the FPGA as a GPIO-Controller ?


Regards,
André


MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
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