From: Alejandro Lucero Palau <alucerop@amd.com>
To: dan.j.williams@intel.com, alejandro.lucero-palau@amd.com,
linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com, dave.jiang@intel.com
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v16 01/22] cxl: Add type2 device basic support
Date: Wed, 21 May 2025 11:44:47 +0100 [thread overview]
Message-ID: <10546cf5-c348-47db-bef7-4bfeeca6cd40@amd.com> (raw)
In-Reply-To: <682c2c6f8398_2b1610050@dwillia2-mobl4.notmuch>
On 5/20/25 08:17, dan.j.williams@intel.com wrote:
> alejandro.lucero-palau@ wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Differentiate CXL memory expanders (type 3) from CXL device accelerators
>> (type 2) with a new function for initializing cxl_dev_state and a macro
>> for helping accel drivers to embed cxl_dev_state inside a private
>> struct.
>>
>> Move structs to include/cxl as the size of the accel driver private
>> struct embedding cxl_dev_state needs to know the size of this struct.
>>
>> Use same new initialization with the type3 pci driver.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> drivers/cxl/core/mbox.c | 11 +-
>> drivers/cxl/core/memdev.c | 32 +++++
>> drivers/cxl/core/pci.c | 1 +
>> drivers/cxl/core/regs.c | 1 +
>> drivers/cxl/cxl.h | 97 +--------------
>> drivers/cxl/cxlmem.h | 88 +-------------
>> drivers/cxl/cxlpci.h | 21 ----
>> drivers/cxl/pci.c | 17 +--
>> include/cxl/cxl.h | 226 +++++++++++++++++++++++++++++++++++
>> include/cxl/pci.h | 23 ++++
>> tools/testing/cxl/test/mem.c | 3 +-
>> 11 files changed, 305 insertions(+), 215 deletions(-)
>> create mode 100644 include/cxl/cxl.h
>> create mode 100644 include/cxl/pci.h
>>
>> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
>> index d72764056ce6..ab994d459f46 100644
>> --- a/drivers/cxl/core/mbox.c
>> +++ b/drivers/cxl/core/mbox.c
>> @@ -1484,23 +1484,20 @@ int cxl_mailbox_init(struct cxl_mailbox *cxl_mbox, struct device *host)
>> }
>> EXPORT_SYMBOL_NS_GPL(cxl_mailbox_init, "CXL");
>>
>> -struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
>> +struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
>> + u16 dvsec)
>> {
>> struct cxl_memdev_state *mds;
>> int rc;
>>
>> - mds = devm_kzalloc(dev, sizeof(*mds), GFP_KERNEL);
>> + mds = cxl_dev_state_create(dev, CXL_DEVTYPE_CLASSMEM, serial, dvsec,
>> + struct cxl_memdev_state, cxlds, true);
> Existing cxl_memdev_state_create() callers expect that any state
> allocation is managed by devres.
>
> It is ok to make cxl_memdev_state_create() manually allocate, but then
> you still need to take care of existing caller expectations.
I'm surprised to see this. I think the expectation was the
cxl_dev_state_create to be managed by devres, and somehow it ended up
without it.
I think the best option here is to add it. I do not think it needs any
special action but just the freeing of that memory.
>> if (!mds) {
>> dev_err(dev, "No memory available\n");
>> return ERR_PTR(-ENOMEM);
>> }
>>
>> mutex_init(&mds->event.log_lock);
>> - mds->cxlds.dev = dev;
>> - mds->cxlds.reg_map.host = dev;
>> - mds->cxlds.cxl_mbox.host = dev;
>> - mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
>> - mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
>>
>> rc = devm_cxl_register_mce_notifier(dev, &mds->mce_notifier);
> Ugh, but this function is now confused as some resources are devm, and
> some are manual alloc. this is a bit of a mess. Like why does this need
> to dev_warn() every boot on MCE-less archs like ARM64?
>
> I was trying to keep the incremental fixup small, but this makes it
> bigger, and likely means we need to clean this up before this patch.
>
> Ugh2, looks like this current arrangment will cause a NULL pointer
> de-reference if an MCE fires between cxl_memdev_state_create() and
> devm_cxl_add_memdev().
>
> Ugh3, looks like the MCE is registered once per memdev, but triggers
> memory_failure() once per spa match. That really wants to be registered
> once per-region.
>
> That whole situation needs a rethink, but for now make the other
> cleanups a TODO.
I can do those TODOs but I do not think that is relevant for the patch.
I mean, you have discovered a problem there but this patch is not
introducing the problem, AFAIK.
>
>> if (rc == -EOPNOTSUPP)
>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>> index a16a5886d40a..6cc732aeb9de 100644
>> --- a/drivers/cxl/core/memdev.c
>> +++ b/drivers/cxl/core/memdev.c
>> @@ -633,6 +633,38 @@ static void detach_memdev(struct work_struct *work)
>>
>> static struct lock_class_key cxl_memdev_key;
>>
>> +void cxl_dev_state_init(struct cxl_dev_state *cxlds, struct device *dev,
>> + enum cxl_devtype type, u64 serial, u16 dvsec,
>> + bool has_mbox)
> As far as I can see this can be static as _cxl_dev_state_create() is the
> only caller in this whole series. Fixup included below:
Sure.
>> +{
>> + *cxlds = (struct cxl_dev_state) {
>> + .dev = dev,
>> + .type = type,
>> + .serial = serial,
>> + .cxl_dvsec = dvsec,
>> + .reg_map.host = dev,
>> + .reg_map.resource = CXL_RESOURCE_NONE,
>> + };
>> +
>> + if (has_mbox)
>> + cxlds->cxl_mbox.host = dev;
>> +}
>> +
>> +struct cxl_dev_state *_cxl_dev_state_create(struct device *dev,
>> + enum cxl_devtype type, u64 serial,
>> + u16 dvsec, size_t size,
>> + bool has_mbox)
>> +{
>> + struct cxl_dev_state *cxlds __free(kfree) = kzalloc(size, GFP_KERNEL);
>> +
>> + if (!cxlds)
>> + return NULL;
>> +
>> + cxl_dev_state_init(cxlds, dev, type, serial, dvsec, has_mbox);
>> + return_ptr(cxlds);
> This function is so simple, there is no need to use scope-based cleanup.
>
OK. I'll do so.
Thanks!
next prev parent reply other threads:[~2025-05-21 10:44 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20 2:43 ` Alison Schofield
2025-05-20 7:18 ` Alejandro Lucero Palau
2025-05-20 20:06 ` Dave Jiang
2025-05-21 9:30 ` Alejandro Lucero Palau
2025-05-20 7:17 ` dan.j.williams
2025-05-21 10:44 ` Alejandro Lucero Palau [this message]
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20 7:37 ` dan.j.williams
2025-05-21 10:50 ` Alejandro Lucero Palau
2025-05-21 17:12 ` Dan Williams
2025-05-22 8:49 ` Alejandro Lucero Palau
2025-05-22 19:41 ` Dan Williams
2025-06-04 8:09 ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20 2:42 ` Alison Schofield
2025-05-21 17:44 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:23 ` Dan Williams
2025-05-22 9:45 ` Alejandro Lucero Palau
2025-05-22 19:51 ` Dan Williams
2025-05-23 9:12 ` Alejandro Lucero Palau
2025-05-23 16:55 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:28 ` Dan Williams
2025-05-22 9:52 ` Alejandro Lucero Palau
2025-05-22 20:04 ` Dan Williams
2025-06-06 11:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34 ` Dan Williams
2025-05-22 10:07 ` Alejandro Lucero Palau
2025-05-22 20:22 ` Dan Williams
2025-05-22 20:53 ` Dan Williams
2025-05-22 21:09 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:47 ` Dan Williams
2025-05-22 10:24 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:49 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 19:31 ` Dan Williams
2025-05-22 10:56 ` Alejandro Lucero Palau
2025-05-22 20:31 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56 ` Dan Williams
2025-06-06 12:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-21 20:23 ` Dan Williams
2025-06-06 13:09 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20 2:38 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-21 20:45 ` Dan Williams
2025-06-06 13:27 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 20:49 ` Dan Williams
2025-06-06 13:39 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01 ` Dan Williams
2025-06-06 13:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20 2:35 ` Alison Schofield
2025-05-21 21:31 ` Dan Williams
2025-06-06 14:03 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48 ` Dan Williams
2025-05-23 1:13 ` Edward Cree
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