From: David Woodhouse <dwmw2@infradead.org>
To: "J.D. Bakker" <bakker@thorgal.et.tudelft.nl>
Cc: linux-mtd@lists.infradead.org
Subject: Re: Handling multiple NAND chips
Date: Fri, 25 Jul 2003 11:51:21 -0400 [thread overview]
Message-ID: <1059148279.28255.43.camel@lapdancer.baythorne.internal> (raw)
In-Reply-To: <a05200f4ebb46f6708c1c@[130.161.115.44]>
On Fri, 2003-07-25 at 11:12, J.D. Bakker wrote:
> Hi all,
>
> I have an expansion board for the LART (an embedded computer based on
> the DEC/Intel StrongARM) with eight NAND flash devices on it. As
> suggested by the Toshiba datasheet, they share data, CLE, ALE, nWE
> and nRE and RDY. Each chip has its own nCE line.
Btw, I suspect that when we come to implement this, we'll find you'd get
much more parallelism if you had _separate_ FR/B# lines for each chip.
If you can hook your FR/B# lines up to an IRQ-capable GPIO, that'd be
cute too.
--
dwmw2
next prev parent reply other threads:[~2003-07-25 15:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-07-25 15:12 Handling multiple NAND chips J.D. Bakker
2003-07-25 15:36 ` David Woodhouse
2003-07-25 15:51 ` J.D. Bakker
2003-07-25 15:56 ` David Woodhouse
2003-07-26 10:22 ` J.D. Bakker
2003-07-26 11:39 ` Thomas Gleixner
2003-07-26 15:08 ` David Woodhouse
2003-07-26 17:20 ` Thomas Gleixner
2003-07-26 15:06 ` David Woodhouse
2003-07-26 18:20 ` J.D. Bakker
2003-07-26 19:05 ` David Woodhouse
2003-07-27 12:54 ` J.D. Bakker
2003-07-27 13:42 ` David Woodhouse
2003-07-27 13:58 ` J.D. Bakker
2003-07-27 16:28 ` David Woodhouse
2003-07-25 15:51 ` David Woodhouse [this message]
2003-07-26 0:27 ` Charles Manning
2003-07-26 10:32 ` J.D. Bakker
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