From: Mike Uhler <uhler@mips.com>
To: David Kesselring <dkesselr@mmc.atmel.com>
Cc: linux-mips@linux-mips.org
Subject: Re: C0 config reg for 5k core
Date: 11 Aug 2003 12:32:08 -0700 [thread overview]
Message-ID: <1060630328.1071.20.camel@uhler-linux.mips.com> (raw)
In-Reply-To: <Pine.GSO.4.44.0308111422220.4449-100000@ares.mmc.atmel.com>
Bit 0 of Config1 is FPU-present. Bit 4 is "Performance counters
present". I guarantee you that the 5K family implements this
pattern.
/gmu
On Mon, 2003-08-11 at 11:28, David Kesselring wrote:
> Has anyone else built linux 2.4 for a 5k or 5kf core? When comparing cpu.h
> and the MIPS64 5K Processor Core Family Software Users Manual it doesn't
> look to me that the c0-config1 reg is defined the same way. Am I reading
> something wrong? For example in the spec FPU flag is bit0 while in cpu.h
> it is bit4. Seems pretty basic.
>
> David Kesselring
> Atmel MMC
> dkesselr@mmc.atmel.com
> 919-462-6587
--
Michael Uhler, Chief Technology Officer
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next prev parent reply other threads:[~2003-08-11 19:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-08-11 18:28 C0 config reg for 5k core David Kesselring
2003-08-11 19:32 ` Mike Uhler [this message]
2003-08-11 19:57 ` David Kesselring
2003-08-11 20:00 ` Mike Uhler
2003-08-12 11:21 ` Chris Dearman
2003-08-12 12:39 ` David Kesselring
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