From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Gabriel Paubert <paubert@iram.es>
Cc: Juergen Kienhoefer <juergen@kienhoefer.com>,
linuxppc-dev list <linuxppc-dev@lists.linuxppc.org>
Subject: Re: cache coherence problem
Date: Wed, 19 Nov 2003 11:35:06 +1100 [thread overview]
Message-ID: <1069202105.31665.4.camel@gaston> (raw)
In-Reply-To: <20031118093711.GB3924@iram.es>
> newly mapped in blank pages,
>
> If you mean zeroed pages for blanked, I believe that it is wrong.
> The reason being that 0 is an invalid instruction so that the code
> would trap in any case.
>
> Maybe I'm wrong, but I seem to remember this as an optimization
> that Paulus implemented some time ago.
And that we had to undo because glibc relied on it, not invalidating
cache lines in some conditions assuming newly mapped zeroed pages
are delivered icache-clean by the kernel.
One of the arguments of the glibc folks for not fixing that was that
it would be a security hole to let stale icache content leak, so the
kernel has to invalidate them anyway.
Ben.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
prev parent reply other threads:[~2003-11-19 0:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-11-18 1:16 cache coherence problem Juergen Kienhoefer
2003-11-18 2:36 ` Matt Porter
2003-11-18 2:38 ` Michael R. Zucca
2003-11-19 22:35 ` linas
2003-11-18 3:02 ` Benjamin Herrenschmidt
2003-11-18 5:00 ` Juergen Kienhoefer
2003-11-18 5:22 ` Benjamin Herrenschmidt
2003-11-18 5:24 ` Benjamin Herrenschmidt
2003-11-18 17:40 ` cache coherence problem: FIXED Juergen Kienhoefer
2003-11-18 8:04 ` cache coherence problem Wolfgang Denk
2003-11-18 9:37 ` Gabriel Paubert
2003-11-19 0:35 ` Benjamin Herrenschmidt [this message]
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