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Subject: Re: [PATCH] x86 bitops.h commentary on instruction reordering
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Date: Sat, 07 Aug 2004 23:16:06 +0100
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On Gwe, 2004-08-06 at 23:33, H. Peter Anvin wrote:
> > > So, there is no platform independent way for doing that in the kernel?
> > Not really. x86 doesnt have such an instruction.
> Actually it does (sfence, lfence, mfence); they only apply to SSE
> loads and stores since all other x86 operations are guaranteed to be
> strictly ordered.

The ordering guarantees on x86 are not completely strict and they refer
to the observed order of store on the bus rather than execution order.
So while code will generate the same observable results as if it was in
order you can get burned on timing suprises in some odd cases. Some of
the devices will even do weakly ordered stores to memory and fix up the
bus transactions by snooping them and spotting the impending problem.

Secondly on PPro and some others there are various chip errata where not
using locking operations _does_ cause observable out of order stores.
Thats why our unlock path for PPro uses lock movb.

Also for pedants only we support IDT Winchips (ancestor of the VIA C3)
which we do run with weak store ordering from an external view (not an
internal one). On those x86 variants the barrier instructions do what
you would expect.

Alan