From: "Martin Schlemmer [c]" <azarah@nosferatu.za.org>
To: gene.heskett@verizon.net
Cc: Linux Kernel Mailing Lists <linux-kernel@vger.kernel.org>,
Denis Vlasenko <vda@port.imtp.ilyichevsk.odessa.ua>,
Tom Vier <tmv@comcast.net>
Subject: Re: Possible dcache BUG [u]
Date: Sun, 29 Aug 2004 16:34:48 +0200 [thread overview]
Message-ID: <1093790088.27951.29.camel@nosferatu.lan> (raw)
In-Reply-To: <200408290948.47890.gene.heskett@verizon.net>
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On Sun, 2004-08-29 at 15:48, Gene Heskett wrote:
> I think, based on the last 25 hours of running both memburn and
> setiathome at a -nice 19, and there have been no errors, that I might
> have stumbled onto a fix.
>
> It seems the dram is marked DDR400, so I was trying to run it that
> way. Unforch, on checking the invoice for the umpteenth time, it
> finally dawned on me that this particular AMD 2800XP is supposedly a
> 333mhz FSB chip, and not rated for use with DDR400 memory. Switching
> the bios setting for the memory to 'auto' from 'spd' seems to effect
> this particular item, and the memory now signs in as DDR333 Dual
> Channel.
>
> And after 25 hours, no errors, nothing unusual in the logs.
>
I work for a supplier here in ZA, and out of experience memory
compatibility can be a vast gray area.
For instance:
1) You have exactly the same Chipset (say nforce2 400's or whatever),
but different vendors that assembles the board (say Asus/MSI and
Gigabyte). You take PC3200 CL3 sticks, and they work fine on the
Asus and MSI, but dont work on the Gigabyte (only one of the long
list of memory issues Gigabyte boards have - in my experience). It
has a lot to do with how the vendor does the timings, etc.
2) You have 4 sticks of Hynix memory, all for have the exact chips on.
Two have the older pcboard layout, and the other two have the newer.
The older ones give intermittant issues on D865GBR (Bayfield boards -
cant remember the exact code) if you try to run them in dual channel
mode, but works fine with only one stick. The board works fine in
dual channel mode with the new revision pcb sticks.
3) P4 SiS chipsets have a bad habit of only running two sticks together
(non-dual channel chipsets ... 645, 650, 651, with identical sticks)
if you clock the memory down to to the bus of the cpu (400mhz cpu
only runs fine with memory at 200 fsb, and 533 with memory at 266 -
remember, its the true speed of the cpu/memory, not the '4x pumped'
one Intel likes to advertise with, or the 'double data rate' speed
memory is advertised with). With a single chip, it usually runs fine
at 333mhz on 533mhz fsb cpu - cant remember with 400mhz cpu.
That was just some examples to show that vendor/revision/config can make
a huge difference, and lots of headaces. In your case, here is a few
points you could look at.
In general the boards I worked with, worked fine with a 333fsb cpu,
running memory at 400mhz. Last I checked, this might be issues:
1) All nforce2 chipsets had a certain errata that caused timing issues
with ddr400 memory with a CL latency of 2. You had to tipically
downclock the memory to 333mhz, or set the CL latency up to 2.5 or
3. Good example is the popular Kingston Hyper-X sticks. I am not
sure if they might have sorted it out on later chipsets.
2) Hynix memory tipically did not work too great, especially in dual
channel mode. The best memory to use was usually the Samsung PC3200
CL3 ones if you did not want to fork too much (except if you had some
of the Gigabyte boards customers brought to us when they only got the
memory from us - do they ever learn not to shop around if it comes to
board and memory?)
3) *sometimes* a bios update did help.
Anyhow, just a few things I ran into that you might have a look at -
sorry its a bit late in this thread.
--
Martin Schlemmer
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next prev parent reply other threads:[~2004-08-29 14:38 UTC|newest]
Thread overview: 144+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-08-02 13:14 Possible dcache BUG Brett Charbeneau
2004-08-05 2:16 ` Gene Heskett
2004-08-05 3:46 ` Andrew Morton
2004-08-05 4:31 ` Gene Heskett
2004-08-05 0:44 ` Chris Shoemaker
2004-08-05 8:35 ` Denis Vlasenko
2004-08-05 14:14 ` Gene Heskett
2004-08-05 13:48 ` Gene Heskett
[not found] ` <200408210118.02011.vda@port.imtp.ilyichevsk.odessa.ua>
2004-08-21 1:40 ` Gene Heskett
2004-08-05 8:33 ` Denis Vlasenko
2004-08-05 14:19 ` Gene Heskett
[not found] ` <200408070203.35268.vda@port.imtp.ilyichevsk.odessa.ua>
2004-08-07 1:28 ` Gene Heskett
2004-08-05 21:26 ` Chris Shoemaker
2004-08-05 7:25 ` Linus Torvalds
2004-08-05 7:31 ` Andrew Morton
2004-08-05 8:33 ` Denis Vlasenko
2004-08-05 14:55 ` Gene Heskett
2004-08-05 16:26 ` Linus Torvalds
2004-08-05 18:06 ` Ingo Molnar
2004-08-05 18:50 ` Linus Torvalds
2004-08-05 20:29 ` Andi Kleen
[not found] ` <20040806073739.GA6617@elte.hu>
[not found] ` <20040806004231.143c8bd2.akpm@osdl.org>
2004-08-06 8:27 ` Ingo Molnar
2004-08-06 11:51 ` Gene Heskett
2004-08-06 16:58 ` Linus Torvalds
2004-08-06 17:16 ` Gene Heskett
2004-08-06 17:26 ` William Lee Irwin III
2004-08-06 23:19 ` Chris Shoemaker
2004-08-07 4:15 ` William Lee Irwin III
2004-08-07 0:05 ` Chris Shoemaker
2004-08-07 5:50 ` William Lee Irwin III
2004-08-06 23:09 ` Chris Shoemaker
2004-08-07 6:20 ` Linus Torvalds
2004-08-07 12:38 ` Gene Heskett
2004-08-07 13:44 ` Chris Shoemaker
2004-08-07 18:49 ` Linus Torvalds
2004-08-07 19:01 ` Gene Heskett
2004-08-06 11:31 ` Andi Kleen
2004-08-06 17:16 ` Linus Torvalds
2004-08-05 21:10 ` Chris Shoemaker
2004-08-06 2:03 ` Gene Heskett
2004-08-06 2:12 ` Gene Heskett
2004-08-06 2:50 ` Linus Torvalds
2004-08-06 3:18 ` viro
2004-08-06 3:24 ` Linus Torvalds
2004-08-08 4:42 ` Gene Heskett
2004-08-08 14:30 ` Gene Heskett
2004-08-08 18:39 ` Andrew Morton
2004-08-10 4:12 ` Gene Heskett
2004-08-11 3:42 ` Gene Heskett
2004-08-11 3:46 ` Linus Torvalds
2004-08-11 4:18 ` Udo A. Steinberg
2004-08-11 5:13 ` Linus Torvalds
2004-08-11 5:15 ` Linus Torvalds
2004-08-11 5:33 ` Udo A. Steinberg
2004-08-11 14:37 ` Gene Heskett
2004-08-12 1:26 ` Nick Piggin
2004-08-12 2:23 ` Gene Heskett
2004-08-12 2:36 ` Nick Piggin
2004-08-13 1:00 ` Udo A. Steinberg
2004-08-13 1:31 ` Linus Torvalds
2004-08-13 2:03 ` Gene Heskett
2004-08-13 2:27 ` Andreas Dilger
2004-08-13 3:33 ` Linus Torvalds
2004-08-20 7:02 ` Udo A. Steinberg
2004-08-20 7:11 ` Andrew Morton
2004-08-20 7:19 ` Udo A. Steinberg
2004-08-20 7:49 ` Nick Piggin
2004-08-24 6:08 ` Udo A. Steinberg
2004-08-24 7:41 ` Nick Piggin
2004-08-24 18:20 ` Marcelo Tosatti
2004-08-24 20:00 ` Andrew Morton
2004-08-24 18:40 ` Marcelo Tosatti
2004-08-25 0:27 ` Marcelo Tosatti
2004-09-12 7:03 ` Udo A. Steinberg
2004-09-12 7:16 ` Andrew Morton
2004-09-12 7:29 ` Udo A. Steinberg
2004-09-12 7:48 ` Andrew Morton
[not found] ` <20040912004812.3544c6de.akpm-3NddpPZAyC0@public.gmane.org>
2004-09-13 4:53 ` Len Brown
2004-09-13 4:53 ` Len Brown
2004-08-11 5:55 ` David S. Miller
2004-08-11 4:47 ` Gene Heskett
2004-08-11 4:59 ` Linus Torvalds
2004-08-11 8:05 ` Roger Luethi
2004-08-13 4:27 ` Gene Heskett
2004-08-13 8:32 ` Gene Heskett
2004-08-14 2:18 ` Marcelo Tosatti
2004-08-14 5:19 ` Gene Heskett
2004-08-14 5:50 ` Gene Heskett
2004-08-14 8:17 ` Gene Heskett
2004-08-15 4:09 ` Gene Heskett
2004-08-15 8:48 ` viro
2004-08-15 9:42 ` Gene Heskett
2004-08-15 17:31 ` Andrew Morton
2004-08-15 17:58 ` Gene Heskett
2004-08-15 9:50 ` Gene Heskett
2004-08-15 10:36 ` viro
2004-08-15 10:10 ` Gene Heskett
2004-08-15 10:37 ` viro
2004-08-15 10:42 ` Gene Heskett
2004-08-15 11:00 ` viro
[not found] ` <200408150704.49312.gene.heskett@verizon.net>
2004-08-15 11:26 ` viro
2004-08-15 17:47 ` Gene Heskett
[not found] ` <200408152257.04773.vda@port.imtp.ilyichevsk.odessa.ua>
2004-08-15 20:33 ` Gene Heskett
[not found] ` <200408160803.15206.vda@port.imtp.ilyichevsk.odessa.ua>
2004-08-16 6:32 ` Gene Heskett
2004-08-16 14:13 ` Gene Heskett
[not found] ` <200408161749.23663.vda@port.imtp.ilyichevsk.odessa.ua>
2004-08-16 15:25 ` Gene Heskett
2004-08-16 22:52 ` Gene Heskett
2004-08-16 23:01 ` viro
2004-08-17 4:44 ` Gene Heskett
2004-08-17 4:58 ` Nick Piggin
2004-08-17 5:26 ` Gene Heskett
2004-08-17 11:57 ` Nick Piggin
2004-08-19 9:41 ` Gene Heskett
2004-08-19 18:36 ` Marcelo Tosatti
2004-08-20 2:38 ` Gene Heskett
2004-08-20 7:33 ` Marcelo Tosatti
2004-08-20 15:06 ` Gene Heskett
2004-08-20 15:43 ` V13
2004-08-20 17:29 ` Gene Heskett
2004-08-20 18:13 ` Marc Ballarin
2004-08-20 20:08 ` Gene Heskett
2004-08-21 9:25 ` Barry K. Nathan
2004-08-21 18:31 ` V13
2004-08-21 18:55 ` Gene Heskett
2004-08-22 11:04 ` Helge Hafting
2004-08-22 11:40 ` Gene Heskett
2004-08-20 20:11 ` R. J. Wysocki
2004-08-20 20:17 ` Gene Heskett
2004-08-22 5:05 ` Gene Heskett
2004-08-22 11:42 ` R. J. Wysocki
2004-08-24 2:34 ` Tom Vier
2004-08-24 3:08 ` Gene Heskett
2004-08-25 1:49 ` Tom Vier
2004-08-25 2:33 ` Gene Heskett
2004-08-25 14:55 ` Martin J. Bligh
2004-08-25 17:23 ` Ryan Cumming
2004-08-25 17:36 ` Martin J. Bligh
2004-08-27 14:01 ` Gene Heskett
2004-08-25 6:13 ` Denis Vlasenko
2004-08-29 13:48 ` Gene Heskett
2004-08-29 14:34 ` Martin Schlemmer [c] [this message]
2004-08-29 15:21 ` Rafael J. Wysocki
2004-08-29 17:23 ` Denis Vlasenko
2004-08-29 22:25 ` Gene Heskett
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