Re: [parisc-linux] Proposal for implementing IRQ affinity

[James Bottomley <James.Bottomley@SteelEye.com>]

On Tue, 2004-08-31 at 11:13, Bjorn Helgaas wrote:
> You could support 32 (or 64) interrupts per processor if you wanted to,
> though I think right now it's only 32 or 64 for the whole system.

Yes, but in order to do the affinity thing, we have to make it appear as
if a single interrupt vector potentially belongs to all CPUs...

> Strictly speaking, iosapics are programmed with a 16-bit ID/EID (not
> an actual EIRR address) and an 8-bit vector (not a 5- or 6-bit bit
> number.)  I think the chipset is responsible for routing the ID/EID
> to the correct processor, and on parisc, probably only 32 (or 64) of
> the 256 possible vectors are usable.  I would guess that in addition
> to routing based on ID/EID, the chipset also translates the vector
> number to a 2^vector mask in the form the EIRR expects.

Yes, I'm sorry, sloppy terminology.  I don't actually have any iosapic
based machines, so I only had to muck with the iosapic once getting an
a500 SMP working...I was going from memory instead of actually looking
in the code.

> I think it would be good if parisc adopted the more generic concepts,
> because it's a shame that ia64 and parisc have such totally different
> code to drive the identical iosapic hardware.

I agree.

James


_______________________________________________
parisc-linux mailing list
parisc-linux@lists.parisc-linux.org
http://lists.parisc-linux.org/mailman/listinfo/parisc-linux