[Qemu-devel] PPC PReP PCI host bridge

[Thayne Harbaugh <thayne@realmsys.com>]

I previously sent a patch to add a PCI host bridge to PPC PReP - it
hasn't been applied.  Currently, PReP lacks a PCI host bridge and only
has a PCI to PCI bridge.  Without a host bridge, PReP doesn't work
correctly.  I'm wondering when a correct host bridge, either the one I
submitted or another one, will be added?  I'd like to know so that
OpenHackWare can be configured to recognize it.


-------- Forwarded Message --------
> From: Thayne Harbaugh <thayne@realmsys.com>

> Index: qemu-0.6.1/hw/pci.c
> ===================================================================
> --- qemu-0.6.1/hw/pci.c	(.../qemu-0.6.1)	(revision 7)
> +++ qemu-0.6.1/hw/pci.c	(.../external/qemu-0.6.1)	(working copy)
> @@ -698,10 +698,25 @@
>                                             PPC_PCIIO_write, s);
>      cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
>  
> -    d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
> -                            NULL, NULL);
> +    /* PCI host bridge */ 
> +    d = pci_register_device(s, "PREP Host Bridge - Motorola Raven", sizeof(PCIDevice), 
> +                            0, NULL, NULL);
> +    d->config[0x00] = 0x57; // vendor_id : Apple
> +    d->config[0x01] = 0x10;
> +    d->config[0x02] = 0x01; // device_id
> +    d->config[0x03] = 0x48;
> +    d->config[0x08] = 0x00; // revision
> +    d->config[0x0A] = 0x00; // class_sub = pci host
> +    d->config[0x0B] = 0x06; // class_base = PCI_bridge
> +    d->config[0x0C] = 0x08; // cache_line_size
> +    d->config[0x0D] = 0x10; // latency_timer
> +    d->config[0x0E] = 0x00; // header_type
> +    d->config[0x34] = 0x00; // capabilities_pointer
>  
> -    /* XXX: put correct IDs */
> +    /* PCI to PCI bridge */
> +    d = pci_register_device(s, "PREP PCI Bridge - Digital 21154", sizeof(PCIDevice),
> +			    0xa0 << 3, NULL, NULL);
> +    /* same values as PearPC - check this */
>      d->config[0x00] = 0x11; // vendor_id
>      d->config[0x01] = 0x10;
>      d->config[0x02] = 0x26; // device_id
> @@ -710,6 +725,7 @@
>      d->config[0x0a] = 0x04; // class_sub = pci2pci
>      d->config[0x0b] = 0x06; // class_base = PCI_bridge
>      d->config[0x0e] = 0x01; // header_type
> +
>      return s;
>  }