From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Stuart Yoder <stuart.yoder@conformative.com>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
Subject: Re: PowerPC + SMP
Date: Tue, 26 Apr 2005 13:36:34 +1000 [thread overview]
Message-ID: <1114486594.7183.12.camel@gaston> (raw)
In-Reply-To: <052701c549db$4fb20760$2f010a0a@foundation.com>
On Mon, 2005-04-25 at 16:11 -0500, Stuart Yoder wrote:
> Hi.
>
> I am trying to figure out where in the PowerPC kernel the HID1
> register is updated to enable bits dealing with cache coherency in an
> SMP system. Grepping through the arch/ppc source does not reveal
> much.
>
> I have two 7447A processors and somewhere the ABE and SYNCBE bits need
> to be turned on to enable cache coherency. Is supposed to happen in
> the bootloader prior to the kernel running??
It's usually expected to happen in the firmware yes, though the kernel
does some of it's own 'fixups' (look at setup_cpu_6xx.S)
Ben.
next prev parent reply other threads:[~2005-04-26 3:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-25 21:11 PowerPC + SMP Stuart Yoder
2005-04-26 3:36 ` Benjamin Herrenschmidt [this message]
2005-04-26 14:54 ` Stuart Yoder
2005-04-26 17:35 ` Wolfgang Denk
2005-04-26 19:07 ` Stuart Yoder
2005-04-26 22:27 ` Benjamin Herrenschmidt
2005-04-26 23:04 ` Paul Mackerras
-- strict thread matches above, loose matches on Subject: below --
2005-04-27 4:37 Frank
2005-04-25 21:10 Stuart Yoder
2005-04-25 21:39 ` Kumar Gala
2005-04-26 19:16 ` Stuart Yoder
2005-04-26 19:23 ` Kumar Gala
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