From: DENX Support System <support@denx.de>
To: u-boot@lists.denx.de
Subject: [DNX#2006040142000811] [U-Boot-Users] Re: [U-Boot-Users][Patch] Cleanup o [...]
Date: Sat, 1 Apr 2006 00:20:35 +0200 [thread overview]
Message-ID: <1143843635.814269.830888911@castor.denx.de> (raw)
Hello list,
inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006040142000811] was created:
<snip>
> Wolfgang Denk ha scritto:
> >>Are there any particular reasons why this code should stay in start.S ?
> >
> >
> > Never change a running system without need?
> >
> Yeah, though not technical is an important one indeed ;-)
> But since a SoC structure has been created I thought it was nice to have
> all the independent
> files cleaned. Just give it a try! Anyway I'll fully understand if you
> prefer not to touch
> a running system.
>
> Best regards
> -P.Broggini
>
>
>
> Signed-off-by: Paolo Broggini <pbroggini@softool.ch>
>
>
> CHANGELOG:
> Cleanup of cpu/arm920t/start.S, S3C24x0 specific code
> moved into boards depended lowlevel_init.s
> Affected boards: sdmk2400, sdmk2410, vcma9, trab
> Patch by Paolo Broggini, 13 Oct 2005
>
>
> diff --git a/board/mpl/vcma9/lowlevel_init.S
> b/board/mpl/vcma9/lowlevel_init.S
> --- a/board/mpl/vcma9/lowlevel_init.S
> +++ b/board/mpl/vcma9/lowlevel_init.S
> @@ -34,6 +34,10 @@
>
> /* some parameters for the board */
>
> +#define pWTCON 0x53000000
> +#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
> +#define INTSUBMSK 0x4A00001C
> +#define CLKDIVN 0x4C000014 /* clock divisor register */
> #define BWSCON 0x48000000
> #define PLD_BASE 0x2C000000
> #define SDRAM_REG 0x2C000106
> @@ -132,6 +136,30 @@ _TEXT_BASE:
>
> .globl lowlevel_init
> lowlevel_init:
> +
> + /*
> + * Watchdog disable
> + */
> + ldr r0, =pWTCON
> + mov r1, #0x0
> + str r1, [r0]
> +
> + /*
> + * mask all IRQs by setting all bits in the INTMR - default
> + */
> + mov r1, #0xffffffff
> + ldr r0, =INTMSK
> + str r1, [r0]
> + ldr r1, =0x3ff
> + ldr r0, =INTSUBMSK
> + str r1, [r0]
> +
> + /* FCLK:HCLK:PCLK = 1:2:4 */
> + /* default FCLK is 120 MHz ! */
> + ldr r0, =CLKDIVN
> + mov r1, #3
> + str r1, [r0]
> +
> /* memory control configuration */
> /* make r0 relative the current location so that it */
> /* reads SMRDATA out of FLASH rather than memory ! */
> diff --git a/board/smdk2400/lowlevel_init.S
> b/board/smdk2400/lowlevel_init.S
> --- a/board/smdk2400/lowlevel_init.S
> +++ b/board/smdk2400/lowlevel_init.S
> @@ -44,9 +44,13 @@
> *
> */
>
> +#define pWTCON 0x15300000
> +#define INTMSK 0x14400008 /* Interupt-Controller base addresses */
> +#define CLKDIVN 0x14800014 /* clock divisor register */
> +
> /* memory controller */
> -#define BWSCON 0x14000000
> -#define BANKCON3 0x14000010 /* for cs8900, ethernet */
> +#define BWSCON 0x14000000
> +#define BANKCON3 0x14000010 /* for cs8900, ethernet */
>
> /* Bank0 */
> #define B0_Tacs 0x0 /* 0 clk */
> @@ -127,6 +131,27 @@ _TEXT_BASE:
>
> .globl lowlevel_init
> lowlevel_init:
> +
> + /*
</snip>
Your U-Boot support team
reply other threads:[~2006-03-31 22:20 UTC|newest]
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