[DNX#2006040142001365] [U-Boot-Users] [PATCH 4/7] Flat device tree suppor [...]

[DENX Support System <support@denx.de>]

Hello list,

inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006040142001365] was created:

<snip>
> * Added support for initializing second PCI bus on 85xx
>   Patch by Andy Fleming 17-Mar-2006
> 
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> 
> ---
> 
>  cpu/mpc85xx/pci.c            |  182
> ++++++++++++++++++++++++++++++++++--------
>  include/asm-ppc/immap_85xx.h |   25 +++++-
> 
> 8f02a97700fadd9e37efdc926f69f6d99e74854b
> diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
> index a94493e..ca11bce 100644
> --- a/cpu/mpc85xx/pci.c
> +++ b/cpu/mpc85xx/pci.c
> @@ -32,66 +32,90 @@
>  
>  #if defined(CONFIG_PCI)
>  
> +static struct pci_controller *pci_hose;
> +
>  void
> -pci_mpc85xx_init(struct pci_controller *hose)
> +pci_mpc85xx_init(struct pci_controller *board_hose)
>  {
> +	u16 reg16;
> +	u32 dev;
> +
>  	volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
>  	volatile ccsr_pcix_t *pcix = &immap->im_pcix;
> +	volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
> +	volatile ccsr_gur_t *gur = &immap->im_gur;
> +	struct pci_controller * hose;
>  
> -	u16 reg16;
> +	pci_hose = board_hose;
> +
> +	hose = &pci_hose[0];
>  
>  	hose->first_busno = 0;
>  	hose->last_busno = 0xff;
>  
> -	pci_set_region(hose->regions + 0,
> -		       CFG_PCI1_MEM_BASE,
> -		       CFG_PCI1_MEM_PHYS,
> -		       CFG_PCI1_MEM_SIZE,
> -		       PCI_REGION_MEM);
> -
> -	pci_set_region(hose->regions + 1,
> -		       CFG_PCI1_IO_BASE,
> -		       CFG_PCI1_IO_PHYS,
> -		       CFG_PCI1_IO_SIZE,
> -		       PCI_REGION_IO);
> -
> -	hose->region_count = 2;
> -
>  	pci_setup_indirect(hose,
>  			   (CFG_IMMR+0x8000),
>  			   (CFG_IMMR+0x8004));
>  
> +	/*
> +	 * Hose scan.
> +	 */
> +	dev = PCI_BDF(hose->first_busno, 0, 0);
> +	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
> +	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
> +	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
> +
> +	/*
> +	 * Clear non-reserved bits in status register.
> +	 */
> +	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
> +
> +	if (!(gur->pordevsr & PORDEVSR_PCI)) {
> +		/* PCI-X init */
> +		reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
> +			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
> +		pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
> +	}
> +
>  	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
>  	pcix->potear1  = 0x00000000;
> -	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
> +	pcix->powbar1  = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
>  	pcix->powbear1 = 0x00000000;
> -	pcix->powar1   = 0x8004401c;	/* 512M MEM space */
> +	pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
> +			POWAR_MEM_WRITE | POWAR_MEM_512M);
>  
> -	pcix->potar2   = 0x00000000;
> +	pcix->potar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
>  	pcix->potear2  = 0x00000000;
> -	pcix->powbar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
> +	pcix->powbar2  = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
>  	pcix->powbear2 = 0x00000000;
> -	pcix->powar2   = 0x80088017;	/* 16M IO space */
> +	pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
> +			POWAR_IO_WRITE | POWAR_IO_1M);
>  
</snip>

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