Re: [PATCH v2 1/1] target/riscv: add VILL field for vtype register macro definition

[Richard Henderson <richard.henderson@linaro.org>]

On 12/11/24 09:48, Chao Liu wrote:
> Signed-off-by: Chao Liu <lc00631@tecorigin.com>
> ---
>   target/riscv/cpu.h | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 284b112821..0d74ee4581 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3)
>   FIELD(VTYPE, VTA, 6, 1)
>   FIELD(VTYPE, VMA, 7, 1)
>   FIELD(VTYPE, VEDIV, 8, 2)
> -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
> +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12)
> +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)

Still incorrect, for the same reason.

We support execution of rv32 cpus with qemu-system-riscv64, where sizeof(target_ulong) is 
always 8.  We support SXL/UXL, which changes the behaviour at runtime.

And, really, why do you want to add a define that is never used?


r~