From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: linux-ia64@vger.kernel.org
Subject: RE: ia64 mmu_gather question
Date: Thu, 02 Aug 2007 22:00:25 +0000 [thread overview]
Message-ID: <1186092025.5495.632.camel@localhost.localdomain> (raw)
In-Reply-To: <1186026055.5495.585.camel@localhost.localdomain>
On Thu, 2007-08-02 at 14:56 -0700, Luck, Tony wrote:
> > So I suspect at this stage that the race isn't affecting you. However,
> > it looks to me that you put the burden on the fairly hot TLB miss path
> > rather than on the much less hot invalidation path itself...
>
> Suggestions on how to do move the burden gratefully received. I don't
> think that it is all that bad though. The re-read of the PGD>PUD>PMD>PTE
> should all hit in the L1-D cache, which has single cycle latency.
Allright. I'll look into it. Other archs have a similar issues and don't
currently fix it. The easy fix for archs that have IPIs for TLB flushes
is to batch the freeing of page tables pages. That's made a bit harder
by the quicklist but I may just end up adding support for those to the
mmu_gather.
Ben.
next prev parent reply other threads:[~2007-08-02 22:00 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-08-02 3:40 ia64 mmu_gather question Benjamin Herrenschmidt
2007-08-02 5:38 ` Luck, Tony
2007-08-02 7:09 ` Benjamin Herrenschmidt
2007-08-02 7:57 ` Benjamin Herrenschmidt
2007-08-02 17:16 ` Luck, Tony
2007-08-02 21:46 ` Benjamin Herrenschmidt
2007-08-02 21:56 ` Luck, Tony
2007-08-02 22:00 ` Benjamin Herrenschmidt [this message]
2007-08-02 22:07 ` David Mosberger-Tang
2007-08-02 22:32 ` Benjamin Herrenschmidt
2007-08-03 3:22 ` Tony Luck
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