From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Mon, 03 Dec 2018 13:25:21 +0100 Message-ID: <11894938.HOUtrQJeEF@phil> References: <20181127074249.15204-1-icenowy@aosc.io> <20181127074249.15204-2-icenowy@aosc.io> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20181127074249.15204-2-icenowy@aosc.io> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: Mark Rutland , devicetree@vger.kernel.org, Jernej Skrabec , Maxime Ripard , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, David Airlie , Chen-Yu Tsai , Rob Herring , Icenowy Zheng List-Id: devicetree@vger.kernel.org QW0gRGllbnN0YWcsIDI3LiBOb3ZlbWJlciAyMDE4LCAwODo0Mjo0OSBDRVQgc2NocmllYiBJY2Vu b3d5IFpoZW5nOgo+IEFsbHdpbm5lciBINiBTb0MgdXNlcyBhIE1hbGkgVDcyMCBHUFUsIHdoaWNo IGlzIG9uZSBvZiB0aGUgR1BVcyBpbiB0aGUKPiBNaWRnYXJkIEdQVSBwcm9kdWN0IGxpbmUuCj4g Cj4gQWRkIGJpbmRpbmcgZm9yIHRoZSBINiBNYWxpIE1pZGdhcmQgR1BVLgo+IAo+IFNpZ25lZC1v ZmYtYnk6IEljZW5vd3kgWmhlbmcgPGljZW5vd3lAYW9zYy5pbz4KPiAtLS0KPiAgLi4uL2Rldmlj ZXRyZWUvYmluZGluZ3MvZ3B1L2FybSxtYWxpLW1pZGdhcmQudHh0ICAgIHwgMTMgKysrKysrKysr KysrKwo+ICAxIGZpbGUgY2hhbmdlZCwgMTMgaW5zZXJ0aW9ucygrKQo+IAo+IGRpZmYgLS1naXQg YS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZ3B1L2FybSxtYWxpLW1pZGdhcmQu dHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2dwdS9hcm0sbWFsaS1taWRn YXJkLnR4dAo+IGluZGV4IDAyZjg3MGNkNjBlNi4uYzg5N2RkN2JlNDhmIDEwMDY0NAo+IC0tLSBh L0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9ncHUvYXJtLG1hbGktbWlkZ2FyZC50 eHQKPiArKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZ3B1L2FybSxtYWxp LW1pZGdhcmQudHh0Cj4gQEAgLTE4LDYgKzE4LDcgQEAgUmVxdWlyZWQgcHJvcGVydGllczoKPiAg ICAgICsgImFtbG9naWMsbWVzb24tZ3htLW1hbGkiCj4gICAgICArICJyb2NrY2hpcCxyazMyODgt bWFsaSIKPiAgICAgICsgInJvY2tjaGlwLHJrMzM5OS1tYWxpIgo+ICsgICAgKyAiYWxsd2lubmVy LHN1bjUwaS1oNi1tYWxpIgoKSSdkIHRoaW5rIHlvdSBtaWdodCB3YW50IHRvIGtlZXAgYW4gYWxw aGFiZXRpY2FsIHNvcnRpbmcgaGVyZSwgYWthCmFib3ZlIGFtbG9naWMsIG90aGVyd2lzZSB0aGUg bGlzdCB3aWxsIHByb2JhYmx5IGJlY29tZSBoYXJkIHRvIHJlYWQKYXQgc29tZSBsYXRlciBwb2lu dC4KCgo+ICAtIHJlZyA6IFBoeXNpY2FsIGJhc2UgYWRkcmVzcyBvZiB0aGUgZGV2aWNlIGFuZCBs ZW5ndGggb2YgdGhlIHJlZ2lzdGVyIGFyZWEuCj4gIAo+IEBAIC00NCw2ICs0NSwxOCBAQCBPcHRp b25hbCBwcm9wZXJ0aWVzOgo+ICAgIGZvciBkZXRhaWxzLgo+ICAKPiAgCj4gK1ZlbmRvci1zcGVj aWZpYyBiaW5kaW5ncwo+ICstLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPiArCj4gK1RoZSBNYWxp IEdQVSBpcyBpbnRlZ3JhdGVkIHZlcnkgZGlmZmVyZW50bHkgZnJvbSBvbmUgU29DIHRvCj4gK2Fu b3RoZXIuIEluIG9yZGVyIHRvIGFjY29tb2RhdGUgdGhvc2UgZGlmZmVyZW5jZXMsIHlvdSBoYXZl IHRoZSBvcHRpb24KPiArdG8gc3BlY2lmeSBvbmUgbW9yZSB2ZW5kb3Itc3BlY2lmaWMgY29tcGF0 aWJsZSwgYW1vbmc6Cj4gKwo+ICsgIC0gYWxsd2lubmVyLHN1bjUwaS1oNi1tYWxpCj4gKyAgICBS ZXF1aXJlZCBwcm9wZXJ0aWVzOgo+ICsgICAgICAqIHJlc2V0czogcGhhbmRsZSB0byB0aGUgcmVz ZXQgbGluZSBmb3IgdGhlIEdQVQoKV2hpbGUgdGhpcyBwYXJhZ3JhcGggaXMgc2ltaWxhciB0byBo b3cgaXQgaXMgZG9uZSBpbiBVdGdhcmQsIEknbQp3b25kZXJpbmcgd2h5IHdlIGNhbm5vdCBqdXN0 IGRlc2NyaWJlIHRoZSAicmVzZXRzIiBhcyByZWd1bGFyCm9wdGlvbmFsIHByb3BlcnR5IGFib3Zl IHRoYXQuCgoKSGVpa28KCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3Rv cC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmkt ZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0211C04EB9 for ; Mon, 3 Dec 2018 12:25:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A025420878 for ; Mon, 3 Dec 2018 12:25:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A025420878 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726496AbeLCM0Z (ORCPT ); Mon, 3 Dec 2018 07:26:25 -0500 Received: from gloria.sntech.de ([185.11.138.130]:47258 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726223AbeLCM0Z (ORCPT ); Mon, 3 Dec 2018 07:26:25 -0500 Received: from we0660.dip.tu-dresden.de ([141.76.178.148] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.0:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1gTnHu-0002aR-08; Mon, 03 Dec 2018 13:25:22 +0100 From: Heiko Stuebner To: dri-devel@lists.freedesktop.org Cc: Icenowy Zheng , Jernej Skrabec , Chen-Yu Tsai , Maxime Ripard , David Airlie , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding Date: Mon, 03 Dec 2018 13:25:21 +0100 Message-ID: <11894938.HOUtrQJeEF@phil> In-Reply-To: <20181127074249.15204-2-icenowy@aosc.io> References: <20181127074249.15204-1-icenowy@aosc.io> <20181127074249.15204-2-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 27. November 2018, 08:42:49 CET schrieb Icenowy Zheng: > Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the > Midgard GPU product line. > > Add binding for the H6 Mali Midgard GPU. > > Signed-off-by: Icenowy Zheng > --- > .../devicetree/bindings/gpu/arm,mali-midgard.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > index 02f870cd60e6..c897dd7be48f 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt > @@ -18,6 +18,7 @@ Required properties: > + "amlogic,meson-gxm-mali" > + "rockchip,rk3288-mali" > + "rockchip,rk3399-mali" > + + "allwinner,sun50i-h6-mali" I'd think you might want to keep an alphabetical sorting here, aka above amlogic, otherwise the list will probably become hard to read at some later point. > - reg : Physical base address of the device and length of the register area. > > @@ -44,6 +45,18 @@ Optional properties: > for details. > > > +Vendor-specific bindings > +------------------------ > + > +The Mali GPU is integrated very differently from one SoC to > +another. In order to accomodate those differences, you have the option > +to specify one more vendor-specific compatible, among: > + > + - allwinner,sun50i-h6-mali > + Required properties: > + * resets: phandle to the reset line for the GPU While this paragraph is similar to how it is done in Utgard, I'm wondering why we cannot just describe the "resets" as regular optional property above that. Heiko