From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Wei Wang2" <wei.wang2@amd.com>
Subject: [PATCH 2/2]Add AMD IOMMU support into hypervisor
Date: Fri, 21 Sep 2007 18:04:26 +0200
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misc.patch: Changes to xen code.

Signed-off-by: Wei Wang <wei.wang2@amd.com>

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diff -r 2477e94450aa xen/arch/x86/hvm/svm/Makefile
--- a/xen/arch/x86/hvm/svm/Makefile	Thu Sep 20 14:15:45 2007 +0100
+++ b/xen/arch/x86/hvm/svm/Makefile	Thu Sep 20 16:39:27 2007 +0200
@@ -1,5 +1,6 @@ subdir-$(x86_32) += x86_32
 subdir-$(x86_32) += x86_32
 subdir-$(x86_64) += x86_64
+subdir-y +=amd_iommu
 
 obj-y += asid.o
 obj-y += emulate.o
diff -r 2477e94450aa xen/arch/x86/setup.c
--- a/xen/arch/x86/setup.c	Thu Sep 20 14:15:45 2007 +0100
+++ b/xen/arch/x86/setup.c	Thu Sep 20 16:39:27 2007 +0200
@@ -1040,6 +1040,8 @@ void __init __start_xen(unsigned long mb
 
     iommu_setup();
 
+    amd_iommu_detect();
+
     /*
      * We're going to setup domain0 using the module(s) that we stashed safely
      * above our heap. The second module, if present, is an initrd ramdisk.
diff -r 2477e94450aa xen/include/asm-x86/fixmap.h
--- a/xen/include/asm-x86/fixmap.h	Thu Sep 20 14:15:45 2007 +0100
+++ b/xen/include/asm-x86/fixmap.h	Thu Sep 20 16:39:27 2007 +0200
@@ -18,6 +18,7 @@
 #include <asm/page.h>
 #include <xen/kexec.h>
 #include <asm/iommu.h>
+#include <asm/amd-iommu.h>
 
 /*
  * Here we define all the compile-time 'special' virtual
@@ -43,6 +44,8 @@ enum fixed_addresses {
       + ((KEXEC_XEN_NO_PAGES >> 1) * KEXEC_IMAGE_NR) - 1,
     FIX_IOMMU_REGS_BASE_0,
     FIX_IOMMU_REGS_END = FIX_IOMMU_REGS_BASE_0 + MAX_IOMMUS-1,
+    FIX_IOMMU_MMIO_BASE_0,
+    FIX_IOMMU_MMIO_END = FIX_IOMMU_MMIO_BASE_0 + IOMMU_PAGES -1,
     __end_of_fixed_addresses
 };
 
diff -r 2477e94450aa xen/include/asm-x86/hvm/iommu.h
--- a/xen/include/asm-x86/hvm/iommu.h	Thu Sep 20 14:15:45 2007 +0100
+++ b/xen/include/asm-x86/hvm/iommu.h	Thu Sep 20 16:39:27 2007 +0200
@@ -42,6 +42,11 @@ struct hvm_iommu {
     spinlock_t mapping_lock;       /* io page table lock */
     int agaw;     /* adjusted guest address width, 0 is level 2 30-bit */
     struct list_head g2m_ioport_list;  /* guest to machine ioport mapping */
+
+    /* amd iommu support */
+    int domain_id;
+    int paging_mode;
+    void *root_table;
 };
 
 #endif // __ASM_X86_HVM_IOMMU_H__

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