[U-Boot-Users] [PATCH 5/5] ppc4xx: Complete PMC440 board support

[Matthias Fuchs <matthias.fuchs@esd-electronics.com>]

This patch brings the PMC440 board configuration file.
Finally it enables the PMC440 board support.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
---
 MAINTAINERS                             |    1 +
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 include/configs/{sequoia.h => PMC440.h} |  400 ++++++++++++++++---------------
 4 files changed, 211 insertions(+), 194 deletions(-)
 copy include/configs/{sequoia.h => PMC440.h} (51%)

diff --git a/MAINTAINERS b/MAINTAINERS
index bf0ebb1..10374ea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -159,6 +159,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 	PCI405			PPC405GP
 	PLU405			PPC405EP
 	PMC405			PPC405GP
+	PMC440			PPC440EPx
 	VOH405			PPC405EP
 	VOM405			PPC405EP
 	WUH405			PPC405EP
diff --git a/MAKEALL b/MAKEALL
index ef181ba..ec43bae 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -208,6 +208,7 @@ LIST_4xx="		\
 	PIP405		\
 	PLU405		\
 	PMC405		\
+	PMC440		\
 	PPChameleonEVB	\
 	rainier		\
 	sbc405		\
diff --git a/Makefile b/Makefile
index 35f8d31..93f5482 100644
--- a/Makefile
+++ b/Makefile
@@ -1234,6 +1234,9 @@ PLU405_config:	unconfig
 PMC405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
 
+PMC440_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
+
 PPChameleonEVB_config		\
 PPChameleonEVB_BA_25_config	\
 PPChameleonEVB_ME_25_config	\
diff --git a/include/configs/sequoia.h b/include/configs/PMC440.h
similarity index 51%
copy from include/configs/sequoia.h
copy to include/configs/PMC440.h
index 72f01d9..165bdca 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/PMC440.h
@@ -1,4 +1,8 @@
 /*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs at esd-electronics.com.
+ * Based on the sequoia configuration file.
+ *
  * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr at denx.de.
  *
@@ -23,7 +27,7 @@
  */
 
 /************************************************************************
- * sequoia.h - configuration for Sequoia & Rainier boards
+ * PMC440.h - configuration for esd PMC440 boards
  ***********************************************************************/
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -31,75 +35,66 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
-#ifndef CONFIG_RAINIER
-#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
-#else
-#define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
-#endif
-#define CONFIG_440		1		/* ... PPC440 family	*/
-#define CONFIG_4xx		1		/* ... PPC4xx family	*/
-/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
-#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
-				33333333 : 33000000)
+#define CONFIG_440EPX		1	/* Specific PPC440EPx   */
+#define CONFIG_440		1	/* ... PPC440 family    */
+#define CONFIG_4xx		1	/* ... PPC4xx family    */
 
-#if 0
-/*
- * 44x dcache supported is working now on sequoia, but we don't enable
- * it yet since it needs further testing
- */
-#define CONFIG_4xx_DCACHE			/* enable dcache	*/
-#endif
+#define CONFIG_SYS_CLK_FREQ	33333400
 
-#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_4xx_DCACHE		/* enable dcache        */
 
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
+#define CONFIG_BOARD_TYPES	1	/* support board types  */
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_LEN		(384  * 1024)	/* Reserve 384 kB for Monitor   */
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
 
 #define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0          */
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH       */
 #define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
-#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_NAND_ADDR		0xd0000000	/* NAND Flash           */
+#define CFG_OCM_BASE		0xe0010000	/* ocm                  */
 #define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
-#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_BASE		0xe0000000	/* Internal PCI regs    */
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
 #define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
 #define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
 #define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_PCI_MEMSIZE		0x80000000	/* 2GB! */
 
 /* Don't change either of these */
-#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals */
 
 #define CFG_USB2D0_BASE		0xe0000100
 #define CFG_USB_DEVICE		0xe0000000
 #define CFG_USB_HOST		0xe0000400
-#define CFG_BCSR_BASE		0xc0000000
+#define CFG_FPGA_BASE0		0xef000000	/* 32 bit */
+#define CFG_FPGA_BASE1		0xef100000	/* 16 bit */
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
-#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM                  */
 #define CFG_INIT_RAM_END	(4 << 10)
-#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_SIZE	256	/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#undef CFG_EXT_SERIAL_CLOCK
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
-/* define this if you want console on UART1 */
-#undef CONFIG_UART1_CONSOLE
+#define CONFIG_SERIAL_MULTI	1
+#undef CONFIG_UART1_CONSOLE	/* console on front panel */
 
 #define CFG_BAUDRATE_TABLE						\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -108,42 +103,52 @@
  * Environment
  *----------------------------------------------------------------------*/
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#define CFG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
 #else
-#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
 #define CFG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
 
 /*-----------------------------------------------------------------------
+ * RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_RX8025
+
+/*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
 
 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection        */
 
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+#define CFG_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
 
 #ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* size of one complete sector          */
 #define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
 
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 #endif
 
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET		0	/* environment starts@the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
+#endif
+
 /*
  * IPL (Initial Program Loader, integrated inside CPU)
  * Will load first 4k from NAND (SPL) into cache and execute it from there.
@@ -162,27 +167,27 @@
  * set up. While still running from cache, I experienced problems accessing
  * the NAND controller.	sr - 2006-08-25
  */
-#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
-#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
+#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
+#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
+#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
+#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 #define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 
 /*
  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  */
-#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
 
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CFG_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CFG_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
+#define CFG_NAND_PAGE_SIZE	512	/* NAND chip page size          */
+#define CFG_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
+#define CFG_NAND_PAGE_COUNT	32	/* NAND chip page count         */
+#define CFG_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
 
 #define CFG_NAND_ECCSIZE	256
 #define CFG_NAND_ECCBYTES	3
@@ -204,131 +209,129 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
+#define CFG_MBYTES_SDRAM	(256)	/* 256MB                        */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
+#define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
 #endif
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address  */
 #define CFG_I2C_SLAVE		0x7F
 
+#define CONFIG_I2C_CMD_TREE	1
+#define CONFIG_I2C_MULTI_BUS	1
+
 #define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+#define CFG_I2C_EEPROM_ADDR		0x54
+#define CFG_I2C_EEPROM_ADDR_LEN		2
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
 
-/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
-#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
-#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
-#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define CFG_DTT_HYSTERESIS	3
+#define CFG_EEPROM_WREN			1
+#define CFG_I2C_BOOT_EEPROM_ADDR	0x52
 
-#define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CFG_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+#define CONFIG_PREBOOT		/* enable preboot variable */
 
 #undef	CONFIG_BOOTARGS
 
 /* Setup some board specific values for the default environment variables */
-#ifndef CONFIG_RAINIER
-#define CONFIG_HOSTNAME		sequoia
-#define CFG_BOOTFILE		"bootfile=/tftpboot/sequoia/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME		rainier
-#define CFG_BOOTFILE		"bootfile=/tftpboot/rainier/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
-#endif
+#define CONFIG_HOSTNAME		pmc440
+#define CFG_BOOTFILE		"bootfile=/tftpboot/pmc440/uImage\0"
+#define CFG_ROOTPATH		"rootpath=/opt/eldk_410/ppc_4xx\0"
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	CFG_BOOTFILE							\
 	CFG_ROOTPATH							\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
+	"nfsroot=${serverip}:${rootpath}\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
+	":${hostname}:${netdev}:off panic=1\0"				\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
+	"bootm ${kernel_addr}\0"					\
 	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"bootm ${kernel_addr} ${ramdisk_addr}\0"			\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
+	"bootm\0"							\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
+	"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"		\
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-		"cp.b 200000 FFFA0000 60000\0"			        \
-	"upd=run load;run update\0"					\
+	"cp.b 200000 FFFA0000 60000\0"					\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
 
-#define CONFIG_M88E1111_PHY	1
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management           */
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics  */
 
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
 #define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NET_MULTI	1
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
 #define CONFIG_PHY1_ADDR	1
+#define CONFIG_RESET_PHY_R	1
 
 /* USB */
-#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
+#define CFG_OHCI_BE_CONTROLLER
+
+#undef CFG_USB_OHCI_BOARD_INIT
+#define CFG_USB_OHCI_CPU_INIT	1
+#define CFG_USB_OHCI_REGS_BASE	CFG_USB_HOST
+#define CFG_USB_OHCI_SLOT_NAME	"ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 
-#endif /* CONFIG_440EPX */
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
@@ -344,62 +347,53 @@
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
-#ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
-#endif
-
-#ifndef CONFIG_RAINIER
-#define CFG_POST_FPU_ON		CFG_POST_FPU
-#else
-#define CFG_POST_FPU_ON		0
-#endif
-
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY   | \
-				 CFG_POST_CPU	   | \
-				 CFG_POST_UART	   | \
-				 CFG_POST_I2C	   | \
-				 CFG_POST_CACHE	   | \
-				 CFG_POST_FPU_ON   | \
-				 CFG_POST_ETHER	   | \
+#define CONFIG_POST		(CFG_POST_MEMORY |	\
+				 CFG_POST_CPU    |	\
+				 CFG_POST_UART   |	\
+				 CFG_POST_I2C    |	\
+				 CFG_POST_CACHE  |	\
+				 CFG_POST_FPU    |	\
+				 CFG_POST_ETHER  |	\
 				 CFG_POST_SPR)
 
 #define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_LOGBUFFER
-#define CFG_POST_CACHE_ADDR	0x10000000 /* free virtual address	*/
+#define CFG_POST_CACHE_ADDR	0x10000000	/* free virtual address     */
 
-#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#define CFG_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
 
 #define CONFIG_SUPPORT_VFAT
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#define CFG_LONGHELP			/* undef to save memory         */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt       */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size      */
 #else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
 #endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16	/* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on          */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
 
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_LOAD_ADDR		0x100000	/* default load address      */
 #define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
+#define CONFIG_LOOPW		1	/* enable loopw command         */
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
@@ -407,18 +401,22 @@
  * PCI stuff
  *----------------------------------------------------------------------*/
 /* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
-#define CFG_PCI_CACHE_LINE_SIZE	0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_PCI		/* include pci support          */
+#define CONFIG_PCI_PNP		/* do (not) pci plug-and-play   */
+#define CFG_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup  */
+#define CFG_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+/* PCI identification */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
+#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
+#define CFG_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
+#define CFG_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
 
 /*
  * For booting Linux, the board info and command line data
@@ -428,6 +426,17 @@
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
+ * FPGA stuff
+ *----------------------------------------------------------------------*/
+#if 0 /* disabled until my FPGA changes will get it into U-Boot :-) */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN2
+#define CONFIG_FPGA_SPARTAN3
+
+#define CONFIG_FPGA_COUNT	2
+#endif
+/*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
 
@@ -435,30 +444,33 @@
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_NAND_CS		2	/* NAND chip connected to CSx   */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
 #define CFG_EBC_PB0AP		0x03017200
 #define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)
 
-/* Memory Bank 3 (NAND-FLASH) initialization					*/
-#define CFG_EBC_PB3AP		0x018003c0
-#define CFG_EBC_PB3CR		(CFG_NAND_ADDR | 0x1c000)
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CFG_EBC_PB2AP		0x018003c0
+#define CFG_EBC_PB2CR		(CFG_NAND_ADDR | 0x1c000)
 #else
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
-/* Memory Bank 3 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB3AP		0x03017200
-#define CFG_EBC_PB3CR		(CFG_FLASH_BASE | 0xda000)
+#define CFG_NAND_CS		0	/* NAND chip connected to CSx   */
+/* Memory Bank 2 (NOR-FLASH) initialization */
+#define CFG_EBC_PB2AP		0x03017200
+#define CFG_EBC_PB2CR		(CFG_FLASH_BASE | 0xda000)
 
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
+/* Memory Bank 0 (NAND-FLASH) initialization */
 #define CFG_EBC_PB0AP		0x018003c0
 #define CFG_EBC_PB0CR		(CFG_NAND_ADDR | 0x1c000)
 #endif
 
-/* Memory Bank 2 (CPLD) initialization						*/
-#define CFG_EBC_PB2AP		0x24814580
-#define CFG_EBC_PB2CR		(CFG_BCSR_BASE | 0x38000)
+/* Memory Bank 4 (FPGA / 32Bit) initialization */
+#define CFG_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
+#define CFG_EBC_PB4CR		(CFG_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
 
-#define CFG_BCSR5_PCI66EN	0x80
+/* Memory Bank 5 (FPGA / 16Bit) initialization */
+#define CFG_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
+#define CFG_EBC_PB5CR		(CFG_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
 
 /*-----------------------------------------------------------------------
  * NAND FLASH
@@ -466,18 +478,18 @@
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
-#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CFG_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
 
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM	0x02	/* Software reboot                      */
 
-#if defined(CONFIG_CMD_KGDB)
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
-#endif	/* __CONFIG_H */
+#endif /* __CONFIG_H */
-- 
1.5.3