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[2003:fa:af00:4300:69d2:56f6:a5af:50a8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4394376118esm2206745e9.40.2025.02.09.04.11.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 09 Feb 2025 04:11:04 -0800 (PST) Date: Sun, 09 Feb 2025 12:10:53 +0000 From: Bernhard Beschow To: BALATON Zoltan , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= CC: qemu-devel@nongnu.org, qemu-block@nongnu.org, Jamin Lin Subject: Re: [PATCH] hw/sd/sdhci: Set reset value of interrupt registers In-Reply-To: References: <20250115190422.5F0FA4E6030@zero.eik.bme.hu> <8cbad5be-e67b-46bd-9198-f7c90ad5ff56@linaro.org> <800dcc1b-8bf6-48e5-843a-99e630d4b494@linaro.org> Message-ID: <11A1B948-8230-4F4B-8809-ECE30A6A34F3@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=shentey@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 6=2E Februar 2025 13:49:38 UTC schrieb BALATON Zoltan : >On Thu, 6 Feb 2025, Philippe Mathieu-Daud=C3=A9 wrote: >> On 6/2/25 13:49, BALATON Zoltan wrote: >>> On Thu, 6 Feb 2025, Philippe Mathieu-Daud=C3=A9 wrote: >>>> On 15/1/25 20:04, BALATON Zoltan wrote: >>>>> The interrupt enable registers are not reset to 0 but some bits are >>>>> enabled on reset=2E At least some U-Boot versions seem to expect thi= s >>>>> and not initialise these registers before expecting interrupts=2E Th= e >>>>> numbers in this patch match what QorIQ P1022 has on reset and fix >>>>> U-Boot for this SoC and should not break other drivers that initiali= se >>>>> (and thus overwrite) these reset values=2E >>>>>=20 >>>>> Signed-off-by: BALATON Zoltan >>>>> --- >>>>> I've also noticed that the work around marked with an XXX comment ne= ar >>>>> line 600 breaks the U-Boot I've tested so I need to disable it: >>>>> if ((s->sdmasysad % boundary_chk) =3D=3D 0) { >>>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 page_aligned =3D true; >>>>> +//=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 page_aligned =3D true; >>>>> } >>>>> What should this hack fix and could it be now removed or somehow >>>>> restricted to cases where it's needed? >>>>=20 >>>> Cc'ing Jamin for >>>> https://lore=2Ekernel=2Eorg/qemu-devel/20241213031205=2E641009-2- jam= in_lin@aspeedtech=2Ecom/ >>>>=20 >>>>>=20 >>>>> hw/sd/sdhci=2Ec | 2 ++ >>>>> =C2=A0 1 file changed, 2 insertions(+) >>>>>=20 >>>>> diff --git a/hw/sd/sdhci=2Ec b/hw/sd/sdhci=2Ec >>>>> index 58375483e3=2E=2E88eb0bfcb2 100644 >>>>> --- a/hw/sd/sdhci=2Ec >>>>> +++ b/hw/sd/sdhci=2Ec >>>>> @@ -303,6 +303,8 @@ static void sdhci_reset(SDHCIState *s) >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->data_count =3D 0; >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->stopped_state =3D sdhc_not_stopped= ; >>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->pending_insert_state =3D false; >>>>> +=C2=A0=C2=A0=C2=A0 s->norintstsen =3D 0x013f; >>>>> +=C2=A0=C2=A0=C2=A0 s->errintstsen =3D 0x117f; >>>>=20 >>>> I guess the problem is earlier: >>>>=20 >>>> =C2=A0=C2=A0 /* >>>> =C2=A0=C2=A0=C2=A0 * Set all registers to 0=2E Capabilities/Version r= egisters are not cleared >>>> =C2=A0=C2=A0=C2=A0 * and assumed to always preserve their value, give= n to them during >>>> =C2=A0=C2=A0=C2=A0 * initialization >>>> =C2=A0=C2=A0=C2=A0 */ >>>> =C2=A0=C2=A0 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintp= tr_t)&s- >sdmasysad); >>>>=20 >>>> Not all registers have to be reset=2E >>>=20 >>> Nothing seems to program those registers before reset but the reset va= lues are documented (for Freescale eSDHCI) to be the above so just not zero= ing them does not seem to be enough=2E Bernhard has similar patch in his br= anch, not sure if he came up with that separately or took this one=2E Do yo= u have some docs on which regs should not be reset? >>=20 >> The header precises what is being modeled here: >>=20 >> * SD Association Host Standard Specification v2=2E0 controller emulatio= n >> * >> * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2=2E= 00=2Epdf >>=20 >> I can not see the reset values you mentioned there=2E >>=20 >> What is wrong with adding a TYPE_FREESCALE_ESDHC, like the >> TYPE_IMX_USDHC / TYPE_S3C_SDHCI types? Then you can add your >> reset handler fixing your fields after sdhci_poweron_reset()=2E > >Nothing's wrong with that, I just did not notice those existing variants= =2E Maybe that's the way to go then with this too=2E Bernhard, do you plan = to do that when cleaning up your tree or should I do another version? Feel free to submit a patch=2E I'm actually in favor of a dedicated device= model which was also my first approach: Perhaps we could have= dedicated source files as well=2E Best regards, Bernhard > >Regards, >BALATON Zoltan