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Sat, 11 May 2024 07:41:07 -0700 (PDT) Message-ID: <11addfd0-d350-4c73-a856-8b7dec2f8ffa@gmail.com> Date: Sat, 11 May 2024 22:41:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string To: "Fea.Wang" , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jim Shu , Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , Max Chou References: <20240510065856.2436870-1-fea.wang@sifive.com> <20240510065856.2436870-2-fea.wang@sifive.com> Content-Language: en-US From: liwei In-Reply-To: <20240510065856.2436870-2-fea.wang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=liwei1518@gmail.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 11 May 2024 10:42:59 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 2024/5/10 14:58, Fea.Wang wrote: > From: Jim Shu > > Public the conversion function of priv_spec and string in cpu.h, so that > tcg-cpu.c could also use it. > > Signed-off-by: Jim Shu > Signed-off-by: Fea.Wang > Reviewed-by: Frank Chang > --- > target/riscv/cpu.c | 4 ++-- > target/riscv/cpu.h | 3 +++ > target/riscv/tcg/tcg-cpu.c | 13 +++++-------- > 3 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a74f0eb29c..b6b48e5620 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1769,7 +1769,7 @@ static const PropertyInfo prop_pmp = { > .set = prop_pmp_set, > }; > > -static int priv_spec_from_str(const char *priv_spec_str) > +int priv_spec_from_str(const char *priv_spec_str) This change seems unnecessary in this patch. Regards, Weiwei Li > { > int priv_version = -1; > > @@ -1784,7 +1784,7 @@ static int priv_spec_from_str(const char *priv_spec_str) > return priv_version; > } > > -static const char *priv_spec_to_str(int priv_version) > +const char *priv_spec_to_str(int priv_version) > { > switch (priv_version) { > case PRIV_VERSION_1_10_0: > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e0dd1828b5..7696102697 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -829,4 +829,7 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, > uint8_t satp_mode_max_from_map(uint32_t map); > const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > +const char *priv_spec_to_str(int priv_version); > +int priv_spec_from_str(const char *priv_spec_str); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 4ebebebe09..faa8de9b83 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -76,16 +76,13 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, > > static const char *cpu_priv_ver_to_str(int priv_ver) > { > - switch (priv_ver) { > - case PRIV_VERSION_1_10_0: > - return "v1.10.0"; > - case PRIV_VERSION_1_11_0: > - return "v1.11.0"; > - case PRIV_VERSION_1_12_0: > - return "v1.12.0"; > + const char *priv_spec_str = priv_spec_to_str(priv_ver); > + > + if (priv_spec_str == NULL) { > + g_assert_not_reached(); > } > > - g_assert_not_reached(); > + return priv_spec_str; > } > > static void riscv_cpu_synchronize_from_tb(CPUState *cs,