Re: [kvm-ppc-devel] [PATCH 3 of 4] [qemu ppc uic] Remember

[Jerone Young <jyoung5@us.ibm.com>]

On Thu, 2008-03-27 at 21:49 -0500, Hollis Blanchard wrote:
> 2 files changed, 9 insertions(+), 2 deletions(-)
> qemu/hw/i8254.c       |    2 ++
> qemu/hw/ppc4xx_devs.c |    9 +++++++--
> 
> 
> # HG changeset patch
> # User Hollis Blanchard <hollisb@us.ibm.com>
> # Date 1206672261 18000
> # Branch merge
> # Node ID 5c61aade5a1cfeecc270f4c0c176709a3a611e87
> # Parent  86c8ce190142bc39927ffaf0cfd8773f04a35086
> [qemu ppc uic] Remember the state of level-triggered interrupts.
> 
> This fixes the following race condition:
> 1. target handles an interrupt and begins to EOI
> 2. device raises an interrupt, setting UIC SR
> 3. target finishes EOI by clearing SR bit
> 
> On hardware, a device with a level-triggered interrupt would instantly
> re-assert SR after step 3, so we need to do the same.
> 
> Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
> 
> diff --git a/qemu/hw/i8254.c b/qemu/hw/i8254.c
> --- a/qemu/hw/i8254.c
> +++ b/qemu/hw/i8254.c
> @@ -27,6 +27,8 @@
>  #include "qemu-timer.h"
> 
>  #include "qemu-kvm.h"
> +
> +#undef KVM_CAP_PIT

Did you mean to keep this in your patch? This file is used by i386 which
does have KVM_CAP_PIT. Did you want to ifdef this ?

> 
>  //#define DEBUG_PIT

> 
> diff --git a/qemu/hw/ppc4xx_devs.c b/qemu/hw/ppc4xx_devs.c
> --- a/qemu/hw/ppc4xx_devs.c
> +++ b/qemu/hw/ppc4xx_devs.c
> @@ -278,6 +278,7 @@ struct ppcuic_t {
>  struct ppcuic_t {
>      uint32_t dcr_base;
>      int use_vectors;
> +    uint32_t level;  /* Remembers the state of level-triggered interrupts. */
>      uint32_t uicsr;  /* Status register */
>      uint32_t uicer;  /* Enable register */
>      uint32_t uiccr;  /* Critical register */
> @@ -385,10 +386,13 @@ static void ppcuic_set_irq (void *opaque
>              uic->uicsr |= mask;
>      } else {
>          /* Level sensitive interrupt */
> -        if (level = 1)
> +        if (level = 1) {
>              uic->uicsr |= mask;
> -        else
> +            uic->level |= mask;
> +        } else {
>              uic->uicsr &= ~mask;
> +            uic->level &= ~mask;
> +	}
>      }
>  #ifdef DEBUG_UIC
>      if (loglevel & CPU_LOG_INT) {
> @@ -460,6 +464,7 @@ static void dcr_write_uic (void *opaque,
>      switch (dcrn) {
>      case DCR_UICSR:
>          uic->uicsr &= ~val;
> +        uic->uicsr |= uic->level;
>          ppcuic_trigger_irq(uic);
>          break;
>      case DCR_UICSRS:
> 
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