[U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS

[York Sun <yorksun@freescale.com>]

Add DIU and cfb console support to FSL 5121ADS board.

Use #define CONFIG_VIDEO in config file to enable fb console.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/ads5121/Makefile      |    2 +-
 board/ads5121/ads5121.c     |   62 ++++++++++++++++-
 board/ads5121/ads5121_diu.c |  165 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/ads5121.h   |   53 +++++++++-----
 4 files changed, 261 insertions(+), 21 deletions(-)
 create mode 100644 board/ads5121/ads5121_diu.c

diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile
index b93bee1..8ace8a1 100644
--- a/board/ads5121/Makefile
+++ b/board/ads5121/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o
+COBJS-y	:= $(BOARD).o ads5121_diu.o ../freescale/common/fsl_diu_fb.o ../freescale/common/fsl_logo_bmp.o
 COBJS-$(CONFIG_PCI) += pci.o
 
 COBJS	:= $(COBJS-y)
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 8629b03..2892665 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -39,17 +39,35 @@
 
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
 			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
 			 CLOCK_SCCR2_I2C_EN)
 
 #define CSAW_START(start)	((start) & 0xFFFF0000)
 #define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
 
+#define MPC5121_IOCTL_PSC6_0	(0x284/4)
+#define MPC5121_IO_DIU_START	(0x288/4)
+#define MPC5121_IO_DIU_END	(0x2fc/4)
+
+/* Functional pin muxing */
+#define MPC5121_IO_FUNC1	(0 << 7)
+#define MPC5121_IO_FUNC2	(1 << 7)
+#define MPC5121_IO_FUNC3	(2 << 7)
+#define MPC5121_IO_FUNC4	(3 << 7)
+#define MPC5121_IO_ST		(1 << 2)
+#define MPC5121_IO_DS_1		(0)
+#define MPC5121_IO_DS_2		(1)
+#define MPC5121_IO_DS_3		(2)
+#define MPC5121_IO_DS_4		(3)
+
 long int fixed_sdram(void);
 
 int board_early_init_f (void)
 {
 	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	u32 lpcaw;
+	u32 lpcaw, tmp32;
+	volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
+	int i;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
@@ -81,6 +99,16 @@ int board_early_init_f (void)
 	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
 	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
 
+	/* Configure DIU clock pin */
+	tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
+	tmp32 &= ~0x1ff;
+	tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
+	ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
+
+	/* Initialize IO pins (pin mux) for DIU function */
+	for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
+		ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
+
 	return 0;
 }
 
@@ -186,6 +214,38 @@ long int fixed_sdram (void)
 	return msize;
 }
 
+int misc_init_r(void)
+{
+	u8 tmp_val;
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	i2c_set_bus_num(2);
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+	ads5121_diu_init();
+#endif
+#endif
+
+	return 0;
+}
+
 int checkboard (void)
 {
 	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
new file mode 100644
index 0000000..87cf0cb
--- /dev/null
+++ b/board/ads5121/ads5121_diu.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "../freescale/common/pixis.h"
+#include "../freescale/common/fsl_diu_fb.h"
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
+
+extern unsigned int FSL_Logo_BMP[];
+
+static int xres, yres;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile clk512x_t *clk = &immap->clk;
+	volatile unsigned int *clkdvdr = &clk->scfr[0];
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0) * 4;
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
+	temp = *clkdvdr & 0xFFFFFF00;
+	*clkdvdr = temp | (pixval & 0x1F);
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
+}
+
+int ads5121_diu_init(void)
+{
+	unsigned int pixel_format;
+
+	xres = 1024;
+	yres = 768;
+	pixel_format = 0x88883316;
+
+	return fsl_diu_init(xres, pixel_format, 0,
+		     (unsigned char *)FSL_Logo_BMP);
+}
+
+int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
+			     int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+
+	if (argc < 2) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (!strncmp(argv[1], "init", 4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+		fsl_diu_clear_screen();
+		drv_video_init();
+#else
+		return ads5121_diu_init();
+#endif
+	} else {
+		addr = simple_strtoul(argv[1], NULL, 16);
+		fsl_diu_clear_screen();
+		fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
+	"diufb init | addr - Init or Display BMP file\n",
+	"init\n    - initialize DIU\n"
+	"addr\n    - display bmp at address 'addr'\n"
+	);
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+	struct fb_info *info;
+
+	if (ads5121_diu_init() < 0)
+		return;
+
+	/* fill in Graphic device struct */
+	sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
+		xres, yres, 32, 64, 60);
+
+	pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+	pGD->winSizeX = xres;
+	pGD->winSizeY = yres - info->logo_height;
+	pGD->plnSizeX = pGD->winSizeX;
+	pGD->plnSizeY = pGD->winSizeY;
+
+	pGD->gdfBytesPP = 4;
+	pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+	pGD->isaBase = 0;
+	pGD->pciBase = 0;
+	pGD->memSize = info->screen_size - info->logo_size;
+
+	/* Cursor Start Address */
+	pGD->dprBase = 0;
+	pGD->vprBase = 0;
+	pGD->cprBase = 0;
+
+	return (void *)pGD;
+}
+
+/**
+  * Set the LUT
+  *
+  * @index: color number
+  * @r: red
+  * @b: blue
+  * @g: green
+  */
+void video_set_lut
+	(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+{
+	return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
+
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 81e7c1e..fb062f1 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -45,14 +45,25 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
 
 /* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
 
 #define CFG_IMMR		0x80000000
+#define CFG_DIU_ADDR		(CFG_IMMR+0x2100)
 
 #define CFG_MEMTEST_START	0x00200000      /* memtest region */
 #define CFG_MEMTEST_END		0x00400000
@@ -127,28 +138,28 @@
 #define CFG_MICRON_OCD_DEFAULT	0x01010780
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2	0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
-#define CFG_MDDRCGRP_LUT0_MU    0x11111117
-#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_PM_CFG1	0x00077777
+#define CFG_MDDRCGRP_PM_CFG2	0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CFG_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU	0x66666666
+#define CFG_MDDRCGRP_LUT1_ML	0x55555555
+#define CFG_MDDRCGRP_LUT2_MU	0x44444444
 #define CFG_MDDRCGRP_LUT2_ML	0x44444444
-#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_MU	0x55555555
 #define CFG_MDDRCGRP_LUT3_ML	0x55555558
-#define CFG_MDDRCGRP_LUT4_MU    0x11111111
-#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU    0x33333377
-#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU    0x11111111
-#define CFG_MDDRCGRP_LUT1_AL	0x11111111
-#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_MU	0x11111111
+#define CFG_MDDRCGRP_LUT4_ML	0x11111122
+#define CFG_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU	0x66666666
+#define CFG_MDDRCGRP_LUT1_AL	0x66666666
+#define CFG_MDDRCGRP_LUT2_AU	0x11111111
 #define CFG_MDDRCGRP_LUT2_AL	0x11111111
-#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AU	0x11111111
 #define CFG_MDDRCGRP_LUT3_AL	0x11111111
-#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AU	0x11111111
 #define CFG_MDDRCGRP_LUT4_AL	0x11111111
 
 /*
@@ -189,7 +200,11 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
 #define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN		(512 * 1024)
+#endif
 
 /*
  * Serial Port
-- 
1.5.2.2