From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH] ARM: dts: rockchip: initialize rk3066 PLL clock rate Date: Tue, 11 Oct 2016 11:19:27 +0200 Message-ID: <12104842.0Sv0KpAWIA@phil> References: <20161006194221.GA4895@vaio-ubuntu> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20161006194221.GA4895@vaio-ubuntu> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: =?utf-8?B?UGF3ZcWC?= Jarosz Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-rockchip.vger.kernel.org QW0gRG9ubmVyc3RhZywgNi4gT2t0b2JlciAyMDE2LCAyMTo0MjoyMSBDRVNUIHNjaHJpZWIgUGF3 ZcWCIEphcm9zejoKPiBJbml0aWFsaXplIFBMTCByYXRlIHdoaWxlIGtlcm5lbCBpbml0LiBObyBv dGhlciBtb2R1bGUgZG9lcyB0aGFuLgo+IENsb2NrIHJhdGVzIGFyZSB0YWtlbiBmcm9tIHJrMzA2 NiBUUk0uIEFzc2lnbmVkIHZhbHVlcyBhcmUgZm9yIDEyNSBkZWdyZWVzCj4gY2VsY2l1cyBvcGVy YXRpbmcgcG9pbnQuCj4gVGhpcyBnaXZlcyB1cyBwZXJmb3JtYW5jZSBib29zdCBvYnNlcnZhYmxl IGZvciBleGFtcGxlIGluIG1tYyB0cmFuc2ZlcnMuCj4gCj4gU2lnbmVkLW9mZi1ieTogUGF3ZcWC IEphcm9zeiA8cGF3ZWxqYXJvc3ozNjkxQGdtYWlsLmNvbT4KPiAtLS0KPiAgYXJjaC9hcm0vYm9v dC9kdHMvcmszMDY2YS5kdHNpIHwgNCArKysrCj4gIDEgZmlsZSBjaGFuZ2VkLCA0IGluc2VydGlv bnMoKykKPiAKPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vYm9vdC9kdHMvcmszMDY2YS5kdHNpIGIv YXJjaC9hcm0vYm9vdC9kdHMvcmszMDY2YS5kdHNpCj4gaW5kZXggMGQwZGFlMy4uY2YyMTVlOCAx MDA2NDQKPiAtLS0gYS9hcmNoL2FybS9ib290L2R0cy9yazMwNjZhLmR0c2kKPiArKysgYi9hcmNo L2FybS9ib290L2R0cy9yazMwNjZhLmR0c2kKPiBAQCAtMTUxLDYgKzE1MSwxMCBAQAo+IAo+ICAJ CSNjbG9jay1jZWxscyA9IDwxPjsKPiAgCQkjcmVzZXQtY2VsbHMgPSA8MT47Cj4gKwkJYXNzaWdu ZWQtY2xvY2tzID0gPCZjcnUgUExMX0RQTEw+LCA8JmNydSBQTExfQVBMTD4sCgp3ZSBzaG91bGRu J3QgdG91Y2ggdGhlIERQTEwgYW5kIEFQTEwgYXQgYWxsIGluIHRoaXMgY29udGV4dC4gVGhleSBh cmUgcXVpdGUgCnJlbGlhbnQgb24gdGhlIHVuZGVybHlpbmcgdm9sdGFnZXMgYW5kIHRoZSBib290 bG9hZGVyIG1pZ2h0J3ZlIHNldCBvdGhlciAKdmFsdWVzLiBBbHNvIGNoYW5naW5nIHRoZSBERFIg ZnJlcXVlbmN5IHRocm91Z2ggdGhlIERQTEwgcmVxdWlyZXMgc3BlY2lhbCAKaGFuZGxpbmcgb24g dGhlIEREUiBzaWRlLgoKPiArCQkJCSAgPCZjcnUgUExMX0NQTEw+LCA8JmNydSBQTExfR1BMTD47 CgpwbGVhc2UgYWxzbyBpbml0aWFsaXplIHRoZSBQRVJJIGFuZCBCVVMgY2xvY2tzIChzaW1pbGFy IHRvIHdoYXQgdGhlIHJrMzI4OCBjbGsgCnNldHRpbmdzIGRvKSwgc28gdGhhdCB0aGV5IHN0YXkg c2FuZSwgZXZlbiBpZiB3ZSBjaGFuZ2UgQ1BMTCBhbmQgR1BMTCAKZnJlcXVlbmNpZXMuCgo+ICsJ CWFzc2lnbmVkLWNsb2NrLXJhdGVzID0gPDUzMzAwMDAwMD4sIDw2MDAwMDAwMDA+LAo+ICsJCQkJ ICAgICAgIDw2MDAwMDAwMDA+LCA8NjAwMDAwMDAwPjsKCkFsc28gc2V0dGluZyBib3RoIENQTEwg YW5kIEdQTEwgdG8gdGhlIHNhbWUgdmFsdWUgbWlnaHQgYmUgdW5oZWxwZnVsIHRvIAphY2hpZXZl IHNwZWNpYWwgZGl2aWRlZCBmcmVxdWVuY2llcz8gQWdhaW4gc2VlIHJrMzI4OC5kdHNpIHdoZXJl IHdlIGhhdmUgYSA1OTQgCi8gNDAwIE1IeiBkaXZpc2lvbi4gRXNwZWNpYWxseSB0aGUgZG93bnN0 cmVhbSBjbG9ja3Mgbm9ybWFsbHkgY2FuIHNlbGVjdCAKYmV0d2VlbiBDUExMIGFuZCBHUExMLgoK CkhlaWtvCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpM aW51eC1yb2NrY2hpcCBtYWlsaW5nIGxpc3QKTGludXgtcm9ja2NoaXBAbGlzdHMuaW5mcmFkZWFk Lm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJv Y2tjaGlwCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko Stuebner) Date: Tue, 11 Oct 2016 11:19:27 +0200 Subject: [PATCH] ARM: dts: rockchip: initialize rk3066 PLL clock rate In-Reply-To: <20161006194221.GA4895@vaio-ubuntu> References: <20161006194221.GA4895@vaio-ubuntu> Message-ID: <12104842.0Sv0KpAWIA@phil> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Am Donnerstag, 6. Oktober 2016, 21:42:21 CEST schrieb Pawe? Jarosz: > Initialize PLL rate while kernel init. No other module does than. > Clock rates are taken from rk3066 TRM. Assigned values are for 125 degrees > celcius operating point. > This gives us performance boost observable for example in mmc transfers. > > Signed-off-by: Pawe? Jarosz > --- > arch/arm/boot/dts/rk3066a.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi > index 0d0dae3..cf215e8 100644 > --- a/arch/arm/boot/dts/rk3066a.dtsi > +++ b/arch/arm/boot/dts/rk3066a.dtsi > @@ -151,6 +151,10 @@ > > #clock-cells = <1>; > #reset-cells = <1>; > + assigned-clocks = <&cru PLL_DPLL>, <&cru PLL_APLL>, we shouldn't touch the DPLL and APLL at all in this context. They are quite reliant on the underlying voltages and the bootloader might've set other values. Also changing the DDR frequency through the DPLL requires special handling on the DDR side. > + <&cru PLL_CPLL>, <&cru PLL_GPLL>; please also initialize the PERI and BUS clocks (similar to what the rk3288 clk settings do), so that they stay sane, even if we change CPLL and GPLL frequencies. > + assigned-clock-rates = <533000000>, <600000000>, > + <600000000>, <600000000>; Also setting both CPLL and GPLL to the same value might be unhelpful to achieve special divided frequencies? Again see rk3288.dtsi where we have a 594 / 400 MHz division. Especially the downstream clocks normally can select between CPLL and GPLL. Heiko