[U-Boot-Users] [PATCH] Blackfin: unify common ADI board settings

[Mike Frysinger <vapier@gentoo.org>]

Rather than duplicate the same ADI settings in every ADI board, create a
common ADI config header and have all ADI boards start using that.  This
will also make merging the ~10 boards I have to forward port a lot easier.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/asm-blackfin/blackfin-config-post.h |   74 +++++-
 include/configs/bf533-ezkit.h               |  246 ++++++-----------
 include/configs/bf533-stamp.h               |  381 +++++++--------------------
 include/configs/bf537-stamp.h               |  359 ++++++++------------------
 include/configs/bf561-ezkit.h               |  283 +++++++-------------
 include/configs/bfin_adi_common.h           |  138 ++++++++++
 6 files changed, 599 insertions(+), 882 deletions(-)
 create mode 100644 include/configs/bfin_adi_common.h

diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h
index 6a1ffa1..d2a413f 100644
--- a/include/asm-blackfin/blackfin-config-post.h
+++ b/include/asm-blackfin/blackfin-config-post.h
@@ -1,7 +1,7 @@
 /*
  * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h
  *
- * Copyright (c) 2007 Analog Devices Inc.
+ * Copyright (c) 2007-2008 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -9,11 +9,6 @@
 #ifndef __ASM_BLACKFIN_CONFIG_POST_H__
 #define __ASM_BLACKFIN_CONFIG_POST_H__
 
-/* Check to make sure everything fits in external RAM */
-#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
-# error Memory Map does not fit into configuration
-#endif
-
 /* Sanity check CONFIG_BFIN_CPU */
 #ifndef CONFIG_BFIN_CPU
 # error CONFIG_BFIN_CPU: your board config needs to define this
@@ -69,4 +64,71 @@
 # define CMD_LINE_ADDR L1_SRAM_SCRATCH
 #endif
 
+/* Default/common Blackfin memory layout */
+#ifndef CFG_SDRAM_BASE
+# define CFG_SDRAM_BASE 0
+#endif
+#ifndef CFG_MAX_RAM_SIZE
+# define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
+#endif
+#ifndef CFG_MEMTEST_START
+# define CFG_MEMTEST_START 0
+#endif
+#ifndef CFG_MEMTEST_END
+# define CFG_MEMTEST_END ((CONFIG_MEM_SIZE - 1) * 1024 * 1024)
+#endif
+#ifndef CFG_MONITOR_BASE
+# define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#endif
+#ifndef CFG_MALLOC_BASE
+# define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#endif
+#ifndef CFG_GBL_DATA_ADDR
+# define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_STACKBASE
+# define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR  - 4)
+#endif
+
+/* Check to make sure everything fits in external RAM */
+#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
+# error Memory Map does not fit into configuration
+#endif
+
+/* Default/common Blackfin environment settings */
+#ifndef CONFIG_LOADADDR
+# define CONFIG_LOADADDR 0x1000000
+#endif
+#ifndef CFG_LOAD_ADDR
+# define CFG_LOAD_ADDR CONFIG_LOADADDR
+#endif
+#ifndef CFG_BOOTM_LEN
+# define CFG_BOOTM_LEN 0x4000000
+#endif
+#ifndef CFG_PROMPT
+# define CFG_PROMPT "bfin> "
+#endif
+#ifndef CFG_CBSIZE
+# if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE 1024
+# else
+#  define CFG_CBSIZE 256
+# endif
+#endif
+#ifndef CFG_BARGSIZE
+# define CFG_BARGSIZE CFG_CBSIZE
+#endif
+#ifndef CFG_PBSIZE
+# define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#endif
+#ifndef CFG_MAXARGS
+# define CFG_MAXARGS 16
+#endif
+#ifndef CFG_HZ
+# define CFG_HZ 1000
+#endif
+#ifndef CFG_BAUDRATE_TABLE
+# define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#endif
+
 #endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index f267301..852b6fd 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -2,139 +2,83 @@
  * U-boot - Configuration file for BF533 EZKIT board
  */
 
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
+#ifndef __CONFIG_BF533_EZKIT_H__
+#define __CONFIG_BF533_EZKIT_H__
 
 #include <asm/blackfin-config-pre.h>
 
-#define CONFIG_BAUDRATE		57600
 
-#define CONFIG_BOOTDELAY	5
-#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-#define CFG_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_LOADADDR		0x01000000	/* default load address */
-#define CONFIG_BOOTCOMMAND	"tftp $(loadaddr) linux"
-/* #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw" */
 
-#define CONFIG_DRIVER_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20310300
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			27000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			22
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
 
-#if 0
-#define	CONFIG_MII
-#define CFG_DISCOVER_PHY
-#endif
 
-#define CONFIG_RTC_BFIN		1
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU	bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
-
-/* CONFIG_CLKIN_HZ is any value in Hz				*/
-#define CONFIG_CLKIN_HZ		27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
-/*						    1=CLKIN/2	*/
-#define CONFIG_CLKIN_HALF	0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
-/*						 1=bypass PLL	*/
-#define CONFIG_PLL_BYPASS	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
-/* Values can range from 1-64					*/
-#define CONFIG_VCO_MULT		22
-/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
-/* Values can be 1, 2, 4, or 8 ONLY				*/
-#define CONFIG_CCLK_DIV		1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15					*/
-#define CONFIG_SCLK_DIV		5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
-/* Values can range from 2-65535				*/
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
-#define CONFIG_SPI_BAUD		2
-#define CONFIG_SPI_BAUD_INITBLOCK	4
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE		32
 
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#define CONFIG_EBIU_SDRRC_VAL	0x398
+#define CONFIG_EBIU_SDGCTL_VAL	0x91118d
+/* Early EZKITs had 32megs, but later have 64megs */
+#if (CONFIG_MEM_SIZE == 64)
+#define CONFIG_EBIU_SDBCTL_VAL	(EBCAW_10 | EBSZ_64 | EBE)
 #else
-#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_EBIU_SDBCTL_VAL	(EBCAW_9 | EBSZ_32 | EBE)
 #endif
 
-#define CONFIG_MEM_SIZE		32	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH	9	/* 8, 9, 10, 11    */
-#define CONFIG_MEM_MT48LC16M16A2TG_75	1
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
 
-#define CONFIG_LOADS_ECHO	1
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for monitor */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc() */
+#define CFG_GBL_DATA_SIZE	0x4000
 
 
 /*
- * BOOTP options
+ * Network Settings
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20310300
+#define SMC91111_EEPROM_INIT()	{ *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
+#define CONFIG_HOSTNAME		bf533-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
 
 
 /*
- * Command line configuration.
+ * Flash Settings
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_DATE
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
-
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)	/* 1 ... 31 MB in DRAM */
-#define	CFG_LOAD_ADDR		0x01000000	/* default load address */
-#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
 #define CFG_FLASH_BASE		0x20000000
 
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-#define CFG_FLASH0_BASE		0x20000000
-#define CFG_FLASH1_BASE		0x20200000
-#define CFG_FLASH2_BASE		0x20280000
 #define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
 #define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
 
@@ -142,73 +86,55 @@
 #define CFG_ENV_ADDR		0x20020000
 #define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
 
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#define POLL_MODE		1
 #define FLASH_TOT_SECT		40
-#define FLASH_SIZE		0x220000
-#define CFG_FLASH_SIZE		0x220000
 
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define	CONFIG_MISC_INIT_R
 
 /*
- * I2C settings
+ * I2C Settings
  * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
  */
 #define CONFIG_SOFT_I2C		1	/* I2C bit-banged */
-/*
- * Software (bit-bang) I2C driver configuration
- */
 #define PF_SCL			PF0
 #define PF_SDA			PF1
 
-#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)	if(bit) { \
-				*pFIO_FLAG_S = PF_SDA; \
-				asm("ssync;"); \
-				} \
-			else    { \
-				*pFIO_FLAG_C = PF_SDA; \
-				asm("ssync;"); \
-				}
-#define I2C_SCL(bit)	if(bit) { \
-				*pFIO_FLAG_S = PF_SCL; \
-				asm("ssync;"); \
-				} \
-			else    { \
-				*pFIO_FLAG_C = PF_SCL; \
-				asm("ssync;"); \
-				}
+#define I2C_INIT       do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
+#define I2C_ACTIVE     do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
+#define I2C_TRISTATE   do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
+#define I2C_READ       ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			*pFIO_FLAG_S = PF_SDA; \
+		else \
+			*pFIO_FLAG_C = PF_SDA; \
+		SSYNC(); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			*pFIO_FLAG_S = PF_SCL; \
+		else \
+			*pFIO_FLAG_C = PF_SCL; \
+		SSYNC(); \
+	} while (0)
 #define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
 
 #define CFG_I2C_SPEED		50000
 #define CFG_I2C_SLAVE		0
 
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
-#define CONFIG_EBIU_SDRRC_VAL  0x398
-#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
-#define CONFIG_EBIU_SDBCTL_VAL 0x13
+/*
+ * Misc Settings
+ */
+#define CONFIG_CMD_CPLBINFO
+#define	CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+
 
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
 
 #include <asm/blackfin-config-post.h>
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 6274a7a..921c11d 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -2,97 +2,77 @@
  * U-boot - Configuration file for BF533 STAMP board
  */
 
-#ifndef __CONFIG_STAMP_H__
-#define __CONFIG_STAMP_H__
+#ifndef __CONFIG_BF533_STAMP_H__
+#define __CONFIG_BF533_STAMP_H__
 
 #include <asm/blackfin-config-pre.h>
 
-#define CONFIG_RTC_BFIN			1
-
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU	bf533-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
 
 /*
- * Board settings
+ * Processor Settings
  */
-#define CONFIG_DRIVER_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20300300
-
-/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES	1
+#define CONFIG_BFIN_CPU             bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-/* Is I2C bit-banged? */
-#define CONFIG_SOFT_I2C		1
 
 /*
- * Software (bit-bang) I2C driver configuration
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  */
-#define PF_SCL			PF3
-#define PF_SDA			PF2
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			11059200
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			36
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
 
-/*
- * Video splash screen support
- */
-#define  CONFIG_VIDEO		0
 
 /*
- * Clock settings
+ * Memory Settings
  */
+#define CONFIG_MEM_ADD_WDTH	11
+#define CONFIG_MEM_SIZE		128
 
-/* CONFIG_CLKIN_HZ is any value in Hz				*/
-#define CONFIG_CLKIN_HZ		11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
-/*						    1=CLKIN/2	*/
-#define CONFIG_CLKIN_HALF	0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
-/*						 1=bypass PLL	*/
-#define CONFIG_PLL_BYPASS	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
-/* Values can range from 1-64					*/
-#define CONFIG_VCO_MULT		36
-/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
-/* Values can be 1, 2, 4, or 8 ONLY				*/
-#define CONFIG_CCLK_DIV		1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15					*/
-#define CONFIG_SCLK_DIV		5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
-/* Values can range from 2-65535				*/
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
-#define CONFIG_SPI_BAUD		2
-#define CONFIG_SPI_BAUD_INITBLOCK	4
+#define CONFIG_EBIU_SDRRC_VAL	0x268
+#define CONFIG_EBIU_SDGCTL_VAL	0x911109
+#define CONFIG_EBIU_SDBCTL_VAL	(EBSZ_128 | EBCAW_11 | EBE)
 
-/*
- * Network settings
- */
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL	0x99B39983
 
-#if (CONFIG_DRIVER_SMC91111)
-#if 0
-#define	CONFIG_MII
-#endif
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for monitor */
+#define CFG_MALLOC_LEN		(384 * 1024)	/* Reserve 384 kB for malloc() (video/spi are big) */
+#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data */
 
-/* network support */
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		STAMP
-#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs
 
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20300300
+#define SMC91111_EEPROM_INIT()	{ *pFIO_DIR = 0x01; *pFIO_FLAG_S = 0x01; SSYNC(); }
+#define CONFIG_HOSTNAME		bf533-stamp
 /* To remove hardcoding and enable MAC storage in EEPROM  */
-/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
-#endif /* CONFIG_DRIVER_SMC91111 */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:b8 */
+
 
 /*
- * Flash settings
+ * Flash Settings
  */
-
 #define CFG_FLASH_CFI		/* The flash is CFI compatible  */
 #define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
 #define	CFG_FLASH_CFI_AMD_RESET
@@ -104,219 +84,71 @@
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CFG_ENV_IS_IN_EEPROM	1
 #define CFG_ENV_OFFSET		0x4000
-#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
 #else
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		0x20004000
 #define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
 #endif
-
 #define	CFG_ENV_SIZE		0x2000
-#define CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 #define	ENV_IS_EMBEDDED
-
-#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
-#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */
-
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	11
-
-/*
- * following timeouts shall be used once the
- * Flash real protection is enabled
- */
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
-#define CONFIG_MEM_MT48LC64M4A2FB_7E	1
-
-#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-
-#define	CFG_SDRAM_BASE		0x00000000
-
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
-#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
-#define CONFIG_LOADADDR		0x01000000
-
-#define CFG_LOAD_ADDR		CONFIG_LOADADDR
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
-#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
-/* Check to make sure everything fits in SDRAM */
-#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
-	#error Memory Map does not fit into configuration
-#endif
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
 #else
-#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#define	ENV_IS_EMBEDDED_CUSTOM
 #endif
 
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
-#endif
-
-/*
- * Command settings
- */
-
-#define CFG_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-
-#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
-
-/* configuration lookup from the BOOTP/DHCP server, */
-/* but not try to load any image using TFTP	    */
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
-		"$(rootpath) console=ttyBF0,57600\0" \
-	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
-		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
-	"ramboot=tftpboot $(loadaddr) linux; " \
-		"run ramargs;run addip;bootelf\0" \
-	"nfsboot=tftpboot $(loadaddr) linux; " \
-		"run nfsargs;run addip;bootelf\0" \
-	"flashboot=bootm 0x20100000\0" \
-	"update=tftpboot $(loadaddr) u-boot.bin; " \
-		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
-		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
-	""
-
-#ifdef CONFIG_SOFT_I2C
-#if (!CONFIG_SOFT_I2C)
-#undef CONFIG_SOFT_I2C
-#endif
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#endif
-
-#if (CONFIG_SOFT_I2C)
-#define CONFIG_CMD_I2C
-#endif
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * Console settings
- */
-
-#define CONFIG_BAUDRATE		57600
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args */
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider		*/
+/* Values can range from 2-65535					*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)				*/
+#define CONFIG_SPI
+#define CONFIG_SPI_BAUD			2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
 
-#define CONFIG_LOADS_ECHO	1
 
 /*
- * I2C settings
+ * I2C Settings
  * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
  */
-#if (CONFIG_SOFT_I2C)
-
-#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)	if(bit) { \
-				*pFIO_FLAG_S = PF_SDA; \
-				asm("ssync;"); \
-				} \
-			else	{ \
-				*pFIO_FLAG_C = PF_SDA; \
-				asm("ssync;"); \
-				}
-#define I2C_SCL(bit)	if(bit) { \
-				*pFIO_FLAG_S = PF_SCL; \
-				asm("ssync;"); \
-				} \
-			else	{ \
-				*pFIO_FLAG_C = PF_SCL; \
-				asm("ssync;"); \
-				}
+#define CONFIG_SOFT_I2C
+#define PF_SCL			PF3
+#define PF_SDA			PF2
+#ifdef CONFIG_SOFT_I2C
+#define I2C_INIT       do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0)
+#define I2C_ACTIVE     do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0)
+#define I2C_TRISTATE   do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0)
+#define I2C_READ       ((*pFIO_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			*pFIO_FLAG_S = PF_SDA; \
+		else \
+			*pFIO_FLAG_C = PF_SDA; \
+		SSYNC(); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			*pFIO_FLAG_S = PF_SCL; \
+		else \
+			*pFIO_FLAG_C = PF_SCL; \
+		SSYNC(); \
+	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
 #define CFG_I2C_SPEED		50000
 #define CFG_I2C_SLAVE		0
-#endif /* CONFIG_SOFT_I2C */
+#endif
+
 
 /*
- * Compact Flash settings
+ * Compact Flash / IDE / ATA Settings
  */
 
 /* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF	1 */
-
-#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
-
-#define CONFIG_MISC_INIT_R	1
+/* #define CONFIG_STAMP_CF */
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_MISC_INIT_R
 #define CONFIG_DOS_PARTITION	1
-/*
- * IDE/ATA stuff
- */
 #undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
 #undef  CONFIG_IDE_LED			/* no led for ide supported */
 #undef  CONFIG_IDE_RESET		/* no reset for ide supported */
@@ -332,41 +164,26 @@
 #define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */
 
 #define CFG_ATA_STRIDE		2
+
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL	0x99B3ffc2
 #endif
 
+
 /*
- * Miscellaneous configurable options
+ * Misc Settings
  */
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_RTC_BFIN
 
-#define	CFG_HZ			1000	/* 1ms time tick */
-
-#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */
-
-#define CONFIG_SPI
+/* FLASH/ETHERNET uses the same async bank */
+#define SHARED_RESOURCES 	1
 
-#ifdef  CONFIG_VIDEO
-#if (CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN	1
-#define CONFIG_SILENT_CONSOLE	1
-#else
-#undef CONFIG_VIDEO
-#endif
-#endif
 
 /*
- * FLASH organization and environment definitions
+ * Pull in common ADI header for remaining command/environment setup
  */
-
-#define CONFIG_EBIU_SDRRC_VAL  0x268
-#define CONFIG_EBIU_SDGCTL_VAL 0x911109
-#define CONFIG_EBIU_SDBCTL_VAL 0x37
-
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
-#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
-#define CF_CONFIG_EBIU_AMBCTL1_VAL		0x99B3ffc2
+#include <configs/bfin_adi_common.h>
 
 #include <asm/blackfin-config-post.h>
 
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 01c2fd2..26483c0 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -2,223 +2,79 @@
  * U-boot - Configuration file for BF537 STAMP board
  */
 
-#ifndef __CONFIG_BF537_H__
-#define __CONFIG_BF537_H__
+#ifndef __CONFIG_BF537_STAMP_H__
+#define __CONFIG_BF537_STAMP_H__
 
 #include <asm/blackfin-config-pre.h>
 
-#define CFG_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_BAUDRATE		57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_BOOTDELAY	5
-/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
-/*#define CONFIG_BF537_STAMP_LEDCMD	1*/
 
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU	bf537-0.2
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
-
-#define CONFIG_BFIN_MAC
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
 
-/* Define if want to do post memory test */
-#undef CONFIG_POST_TEST
-
-#define CONFIG_RTC_BFIN		1
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz				*/
-#define CONFIG_CLKIN_HZ		25000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
-/*						    1=CLKIN/2	*/
-#define CONFIG_CLKIN_HALF	0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
-/*						    1=bypass PLL*/
-#define CONFIG_PLL_BYPASS	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
-/* Values can range from 1-64					*/
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
 #define CONFIG_VCO_MULT			20
-/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
-/* Values can be 1, 2, 4, or 8 ONLY				*/
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
 #define CONFIG_CCLK_DIV			1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
-/* Values can range from 1-15					*/
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
 #define CONFIG_SCLK_DIV			5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
-/* Values can range from 2-65535				*/
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
-#define CONFIG_SPI_BAUD			2
-#define CONFIG_SPI_BAUD_INITBLOCK	4
 
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
 
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-#endif
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
 
-#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH		10	/* 8, 9, 10, 11 */
-#define CONFIG_MEM_MT48LC32M8A2_75	1
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL	(EBSZ_64 | EBCAW_10 | EBE)
 
-#define CONFIG_LOADS_ECHO		1
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for monitor */
+#define CFG_MALLOC_LEN		(384 * 1024)	/* Reserve 384 kB for malloc() (video/spi are big) */
+#define CFG_GBL_DATA_SIZE	0x4000
 
-/*
- * rarpb, bootp or dhcp commands will perform only a
- * configuration lookup from the BOOTP/DHCP server
- * but not try to load any image using TFTP
- */
-#define CFG_AUTOLOAD			"no"
 
 /*
  * Network Settings
  */
-/* network support */
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		BF537
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
 #endif
-
-#define CONFIG_ROOTPATH		/romfs
+#define CONFIG_HOSTNAME		bf537-stamp
 /* Uncomment next line to use fixed MAC address */
 /* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
-/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
-
-#define CFG_LONGHELP		1
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-
-#if defined(CONFIG_POST_TEST)
-/* POST support */
-#define CONFIG_POST		( CFG_POST_MEMORY | \
-				  CFG_POST_UART	  | \
-				  CFG_POST_FLASH  | \
-				  CFG_POST_ETHER  | \
-				  CFG_POST_LED	  | \
-				  CFG_POST_BUTTON)
-#else
-#undef CONFIG_POST
-#endif
 
-#ifdef CONFIG_POST
-#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
-#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
-#endif
-
-/* CF-CARD IDE-HDD Support */
-
-/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
-/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
-/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */
-
-#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
-# define CONFIG_BFIN_IDE	1
-#endif
-
-/*#define CONFIG_BF537_NAND */		/* Add nand flash support */
-
-#define CONFIG_NETCONSOLE	1
-#define CONFIG_NET_MULTI	1
 
 /*
- * BOOTP options
+ * Flash Settings
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-
-#ifndef CONFIG_BFIN_MAC
-#undef CONFIG_CMD_NET
-#else
-#define CONFIG_CMD_PING
-#endif
-
-#if defined(CONFIG_BFIN_CF_IDE) \
-	|| defined(CONFIG_BFIN_HDD_IDE) \
-	|| defined(CONFIG_BFIN_TRUE_IDE)
-#define CONFIG_CMD_IDE
-#endif
-
-#define CONFIG_CMD_DHCP
-
-#if defined(CONFIG_POST)
-#define CONFIG_CMD_DIAG
-#endif
-
-#ifdef CONFIG_BF537_NAND
-#define CONFIG_CMD_NAND
-#endif
-
-
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
-#define CONFIG_LOADADDR	0x1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
-	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
-	"addip=setenv bootargs $(bootargs) "			\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-	":$(hostname):eth0:off\0"				\
-	"ramboot=tftpboot $(loadaddr) linux;"			\
-	"run ramargs;run addip;bootelf\0"			\
-	"nfsboot=tftpboot $(loadaddr) linux;"			\
-	"run nfsargs;run addip;bootelf\0"			\
-	"flashboot=bootm 0x20100000\0"				\
-	"update=tftpboot $(loadaddr) u-boot.bin;"		\
-	"protect off 0x20000000 0x2007FFFF;"			\
-	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
-	""
-
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024*1024)
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x0	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
-#define	CFG_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
-#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define	CFG_SDRAM_BASE		0x00000000
-
 #define CFG_FLASH_BASE		0x20000000
 #define CFG_FLASH_CFI		/* The flash is CFI compatible */
 #define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver */
@@ -226,14 +82,6 @@
 #define CFG_MAX_FLASH_BANKS	1
 #define CFG_MAX_FLASH_SECT	71	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
 
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CFG_ENV_IS_IN_EEPROM	1
 #define CFG_ENV_OFFSET		0x4000
@@ -245,29 +93,36 @@
 #endif
 #define CFG_ENV_SIZE		0x2000
 #define	CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
 #define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
 
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	15
-
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider		*/
+/* Values can range from 2-65535					*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)				*/
 #define CONFIG_SPI
+#define CONFIG_SPI_BAUD			2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
+
 
 /*
- * Stack sizes
+ * I2C Settings
  */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C		1	/* I2C TWI */
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0
 
-#define POLL_MODE		1
-#define FLASH_TOT_SECT		71
-#define FLASH_SIZE		0x400000
-#define CFG_FLASH_SIZE		0x400000
 
 /*
- * Board NAND Infomation
+ * NAND Settings
  */
+/* #define CONFIG_BF537_NAND */
+#ifdef CONFIG_BF537_NAND
+# define CONFIG_CMD_NAND
+#endif
 
 #define CFG_NAND_ADDR		0x20212000
 #define CFG_NAND_BASE		CFG_NAND_ADDR
@@ -281,12 +136,12 @@
 #define NAND_MAX_CHIPS		1
 #define BFIN_NAND_READY		PF3
 
-#define NAND_WAIT_READY(nand)			\
-	do {					\
-		int timeout = 0;		\
-		while(!(*pPORTFIO & PF3))	\
-			if (timeout++ > 100000)	\
-				break;		\
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int timeout = 0; \
+		while (!(*pPORTFIO & PF3)) \
+			if (timeout++ > 100000) \
+				break; \
 	} while (0)
 
 #define BFIN_NAND_CLE		(1<<2)	/* A2 -> Command Enable */
@@ -297,40 +152,18 @@
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
-
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
 /*
- * I2C settings
+ * CF-CARD IDE-HDD Support
  */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_BFIN_TWI_I2C	1
-#define CFG_I2C_SPEED		50000
-#define CFG_I2C_SLAVE		0
-
-#define CONFIG_EBIU_SDRRC_VAL  0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x25
-
-#define CONFIG_EBIU_AMGCTL_VAL		0xFF
-#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
-				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
-				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
+/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
+/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
+/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */
 
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0x7BB07BB0
-#define AMBCTL1VAL		0xFFC27BB0
+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE	1
+# define CONFIG_CMD_IDE
+#endif
 
 #if defined(CONFIG_BFIN_IDE)
 
@@ -345,8 +178,8 @@
 #define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
 #define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */
 
-#undef  AMBCTL1VAL
-#define AMBCTL1VAL		0xFFC3FFC3
+#undef  CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3
 
 #define CONFIG_CF_ATASEL_DIS	0x20311800
 #define CONFIG_CF_ATASEL_ENA	0x20311802
@@ -387,6 +220,30 @@
 
 #endif				/*CONFIG_BFIN_IDE */
 
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+
+/* #define CONFIG_BF537_STAMP_LEDCMD	1 */
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
+#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
 #include <asm/blackfin-config-post.h>
 
 #endif
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index e99e979..427a213 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -2,229 +2,146 @@
  * U-boot - Configuration file for BF561 EZKIT board
  */
 
-#ifndef __CONFIG_EZKIT561_H__
-#define __CONFIG_EZKIT561_H__
+#ifndef __CONFIG_BF561_EZKIT_H__
+#define __CONFIG_BF561_EZKIT_H__
 
 #include <asm/blackfin-config-pre.h>
 
-#define CFG_LONGHELP		1
-#define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_BAUDRATE		57600
-/* Set default serial console for bf537 */
-#define CONFIG_UART_CONSOLE	0
-#define CONFIG_EZKIT561		1
-#define CONFIG_BOOTDELAY	5
 
-#define CONFIG_PANIC_HANG 1
-
-#define CONFIG_BFIN_CPU	bf561-0.3
-#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
-/* This sets the default state of the cache on U-Boot's boot */
-#define CONFIG_ICACHE_ON
-#define CONFIG_DCACHE_ON
 
 /*
- * Board settings
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  */
-#define CONFIG_DRIVER_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x2C010300
-#define CONFIG_ASYNC_EBIU_BASE	CONFIG_SMC91111_BASE & ~(4*1024*1024)
-#define CONFIG_SMC_USE_32_BIT	1
-#define CONFIG_MISC_INIT_R	1
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			6
+
 
 /*
- * Clock settings
+ * Memory Settings
  */
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL	0x15
+
+#define CONFIG_EBIU_AMGCTL_VAL	0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for monitor */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc() */
+#define CFG_GBL_DATA_SIZE	0x4000
 
-/* CONFIG_CLKIN_HZ is any value in Hz				*/
-#define CONFIG_CLKIN_HZ		30000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
-/*						    1=CLKIN/2	*/
-#define CONFIG_CLKIN_HALF	0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
-/*						 1=bypass PLL	*/
-#define CONFIG_PLL_BYPASS	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is	*/
-/* Values can range from 1-64					*/
-#define CONFIG_VCO_MULT		20
-/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
-/* Values can be 1, 2, 4, or 8 ONLY				*/
-#define CONFIG_CCLK_DIV		1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15					*/
-#define CONFIG_SCLK_DIV		5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
-/* Values can range from 2-65535				*/
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
-#define CONFIG_SPI_BAUD		2
-#define CONFIG_SPI_BAUD_INITBLOCK	4
 
 /*
- * Network settings
+ * Network Settings
  */
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		ezkit561
-#define CONFIG_ROOTPATH		/arm-cross-build/BF561/uClinux-dist/romfs
-#endif				/* CONFIG_DRIVER_SMC91111 */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x2C010300
+#define CONFIG_SMC_USE_32_BIT	1
+#define CONFIG_HOSTNAME		bf561-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
 
 /*
- * Flash settings
+ * Flash Settings
  */
-
 #define CFG_FLASH_CFI		/* The flash is CFI compatible */
 #define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver */
 #define CFG_FLASH_CFI_AMD_RESET
-#define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_FLASH_BASE		0x20000000
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
-#define CFG_ENV_ADDR		0x20020000
+/* The BF561-EZKIT uses a top boot flash */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE		0x2000
 #define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR	8
-
-/*
- * SDRAM settings & memory map
- */
-
-#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH		9	/* 8, 9, 10, 11    */
-#define CONFIG_MEM_MT48LC16M16A2TG_75	1
-
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
-
-#define CFG_MEMTEST_START	0x0	/* memtest works on */
-#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
-
-#define	CONFIG_LOADADDR		0x01000000	/* default load address */
-#define CFG_LOAD_ADDR		CONFIG_LOADADDR
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
 #else
-#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#define ENV_IS_EMBEDDED_CUSTOM
 #endif
 
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
-#endif
-
-/*
- * Command settings
- */
-
-#define CFG_AUTOLOAD	"no"	/* rarpb, bootp, dhcp commands will	*/
-				/* only perform a configuration		*/
-				/* lookup from the BOOTP/DHCP server	*/
-				/* but not try to load any image	*/
-				/* using TFTP				*/
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, */
-					/* currently its disabled */
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
-
-#if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):"	\
-		"$(rootpath) console=ttyBF0,57600\0"			\
-	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):"	\
-		"$(gatewayip):$(netmask):$(hostname):eth0:off\0"	\
-	"ramboot=tftpboot $(loadaddr) linux; "				\
-		"run ramargs; run addip; bootelf\0"			\
-	"nfsboot=tftpboot $(loadaddr) linux; "				\
-		"run nfsargs; run addip; bootelf\0"			\
-	"update=tftpboot $(loadaddr) u-boot.bin; "			\
-		"protect off 0x20000000 0x2003FFFF; "			\
-		"erase 0x20000000 0x2003FFFF; "				\
-		"cp.b $(loadaddr) 0x20000000 $(filesize)\0"		\
-	""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
-	"flashboot=bootm 0x20100000\0"					\
-	""
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_JFFS2
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
 
-#if defined(CONFIG_DRIVER_SMC91111)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#endif
 
 /*
- * Console settings
+ * I2C Settings
  */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size */
-#else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CONFIG_SOFT_I2C		1
+#define PF_SCL			0x1/*PF0*/
+#define PF_SDA			0x2/*PF1*/
+
+#ifdef CONFIG_SOFT_I2C
+#define I2C_INIT       do { *pFIO0_DIR |= PF_SCL; SSYNC(); } while (0)
+#define I2C_ACTIVE     do { *pFIO0_DIR |= PF_SDA; *pFIO0_INEN &= ~PF_SDA; SSYNC(); } while (0)
+#define I2C_TRISTATE   do { *pFIO0_DIR &= ~PF_SDA; *pFIO0_INEN |= PF_SDA; SSYNC(); } while (0)
+#define I2C_READ       ((*pFIO0_FLAG_D & PF_SDA) != 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			*pFIO0_FLAG_S = PF_SDA; \
+		else \
+			*pFIO0_FLAG_C = PF_SDA; \
+		SSYNC(); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			*pFIO0_FLAG_S = PF_SCL; \
+		else \
+			*pFIO0_FLAG_C = PF_SCL; \
+		SSYNC(); \
+	} while (0)
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0
 #endif
-#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define	CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CONFIG_LOADS_ECHO	1
 
 /*
- * Miscellaneous configurable options
+ * Misc Settings
  */
-#define	CFG_HZ			1000		/* decrementer freq: 10 ms ticks */
-#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+#define CONFIG_CMD_CPLBINFO
+
 
 /*
- * FLASH organization and environment definitions
+ * Pull in common ADI header for remaining command/environment setup
  */
-#define CONFIG_EBIU_SDRRC_VAL  0x306
-#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
-#define CONFIG_EBIU_SDBCTL_VAL 0x15
-
-#define CONFIG_EBIU_AMGCTL_VAL		0x3F
-#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
-#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+#include <configs/bfin_adi_common.h>
 
 #include <asm/blackfin-config-post.h>
 
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
new file mode 100644
index 0000000..0f6524d
--- /dev/null
+++ b/include/configs/bfin_adi_common.h
@@ -0,0 +1,138 @@
+/*
+ * U-Boot - Common settings for Analog Devices boards
+ */
+
+#ifndef __CONFIG_BFIN_ADI_COMMON_H__
+#define __CONFIG_BFIN_ADI_COMMON_H__
+
+/*
+ * Command Settings
+ */
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+# if ADI_CMDS_NETWORK
+#  define CONFIG_CMD_DHCP
+#  define CONFIG_CMD_PING
+# else
+#  undef CONFIG_CMD_NET
+#  undef CONFIG_CMD_NFS
+# endif
+# ifdef CONFIG_RTC_BFIN
+#  define CONFIG_CMD_DATE
+# endif
+# ifdef CONFIG_POST
+#  define CONFIG_CMD_DIAG
+# endif
+# ifdef CONFIG_SPI
+#  define CONFIG_CMD_EEPROM
+# endif
+# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#  define CONFIG_CMD_I2C
+# endif
+# ifndef CFG_NO_FLASH
+#  define CONFIG_CMD_JFFS2
+# endif
+# define CFG_CMD_CACHE
+# define CFG_CMD_ELF
+#endif
+
+/*
+ * Console Settings
+ */
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_LOADS_ECHO	1
+#ifndef CONFIG_BAUDRATE
+# define CONFIG_BAUDRATE	57600
+#endif
+
+/*
+ * Debug Settings
+ */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_DEBUG_DUMP	1
+#define CONFIG_DEBUG_DUMP_SYMS	1
+#define CONFIG_PANIC_HANG	1
+
+/*
+ * Env Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY	-1
+#else
+# define CONFIG_BOOTDELAY	5
+#endif
+#ifndef CONFIG_UART_CONSOLE
+# define CONFIG_UART_CONSOLE	0
+#endif
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#ifdef CONFIG_VIDEO
+# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
+#else
+# define CONFIG_BOOTARGS_VIDEO ""
+#endif
+#define CONFIG_BOOTARGS	\
+	"root=/dev/mtdblock0 rw " \
+	"earlyprintk=serial,uart" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) " " \
+	CONFIG_BOOTARGS_VIDEO \
+	"console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+#ifndef CFG_PROMPT
+# define CFG_PROMPT		"bfin> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#  define UBOOT_ENV_FILE "u-boot.bin"
+# else
+#  define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#  define UBOOT_ENV_UPDATE \
+		"eeprom write $(loadaddr) 0x0 $(filesize)"
+# else
+#  define UBOOT_ENV_UPDATE \
+		"protect off 0x20000000 0x2003FFFF;" \
+		"erase 0x20000000 0x2003FFFF;" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
+# define NETWORK_ENV_SETTINGS \
+	"ubootfile=" UBOOT_ENV_FILE "\0" \
+	"update=" \
+		"tftp $(loadaddr) $(ubootfile);" \
+		UBOOT_ENV_UPDATE \
+		"\0" \
+	"addip=set bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"ramboot=" \
+		"tftp $(loadaddr) uImage;" \
+		"run ramargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0" \
+	"nfsargs=set bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3\0" \
+	"nfsboot=" \
+		"tftp $(loadaddr) vmImage;" \
+		"run nfsargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	"flashboot=bootm 0x20100000\0"
+
+/*
+ * Network Settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+# define CONFIG_IPADDR		192.168.0.15
+# define CONFIG_NETMASK		255.255.255.0
+# define CONFIG_GATEWAYIP	192.168.0.1
+# define CONFIG_SERVERIP	192.168.0.2
+# define CONFIG_ROOTPATH	/romfs
+#endif
+
+#endif
-- 
1.5.5.3