[U-Boot] [PATCH] Fix compiler warning in mpc8xxx ddr code

[Kumar Gala <galak@kernel.crashing.org>]

ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here

Add a warning in DDR1 case if cas_latency isn't a value we know about.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index ca67551..e6c2a5c 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -520,7 +520,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int wr;	/* Write Recovery */
 	unsigned int dll_res;	/* DLL Reset */
 	unsigned int mode;	/* Normal=0 or Test=1 */
-	unsigned int caslat;	/* CAS# latency */
+	unsigned int caslat = 0;/* CAS# latency */
 	/* BT: Burst Type (0=Sequential, 1=Interleaved) */
 	unsigned int bt;
 	unsigned int bl;	/* BL: Burst Length */
@@ -572,7 +572,9 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 			0x6,	/* 2.5 clocks */
 			0x3	/* 3.0 clocks */
 		};
-	caslat = mode_caslat_table[cas_latency - 1];
+		caslat = mode_caslat_table[cas_latency - 1];
+	} else {
+		printf("Warning: unknown cas_latency %d\n", cas_latency);
 	}
 #elif defined(CONFIG_FSL_DDR2)
 	caslat = cas_latency;
-- 
1.5.5.1