From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0583AC77B7F for ; Sat, 13 May 2023 18:40:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229611AbjEMSkO (ORCPT ); Sat, 13 May 2023 14:40:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229508AbjEMSkN (ORCPT ); Sat, 13 May 2023 14:40:13 -0400 X-Greylist: delayed 448 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sat, 13 May 2023 11:40:10 PDT Received: from vulcan.natalenko.name (vulcan.natalenko.name [104.207.131.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FB272139; Sat, 13 May 2023 11:40:10 -0700 (PDT) Received: from spock.localnet (unknown [83.148.33.151]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vulcan.natalenko.name (Postfix) with ESMTPSA id 3E98A130F201; Sat, 13 May 2023 20:32:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=natalenko.name; s=dkim-20170712; t=1684002754; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vRMdV3qzOVMwmQcnB02GoMJuuadMUEoFe1zlRRYP5Zw=; b=BYkiLxOIWN8IVtlF+nUBPTMaSvVLLm07F0DHp73Z+Eb7fP5wfHLu6+z3tHtGudVAjPmDGo cMZS4YuquHcnYJ9oS7feOQiSz26jdOO3YZzY3i1btzZDXY+EaLoZDj8CRG0dAnOPQirDG2 m5QBpNJvNrr34slkYe3VXn3/zoEgtxo= From: Oleksandr Natalenko To: LKML , Thomas Gleixner Cc: x86@kernel.org, David Woodhouse , Andrew Cooper , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Tom Lendacky , Sean Christopherson , Paul Menzel , "Guilherme G. Piccoli" , Piotr Gorski , Usama Arif , Juergen Gross , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E.J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland , Sabin Rapan , "Michael Kelley (LINUX)" , Ross Philipson Subject: Re: [patch V4 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup Date: Sat, 13 May 2023 20:32:31 +0200 Message-ID: <12207466.O9o76ZdvQC@natalenko.name> In-Reply-To: <20230512203426.452963764@linutronix.de> References: <20230512203426.452963764@linutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org Hello. On p=C3=A1tek 12. kv=C4=9Btna 2023 23:06:56 CEST Thomas Gleixner wrote: > Hi! >=20 > This is version 4 of the reworked parallel bringup series. Version 3 can = be > found here: >=20 > https://lore.kernel.org/lkml/20230508181633.089804905@linutronix.de >=20 > This is just a reiteration to address the following details: >=20 > 1) Address review feedback (Peter Zijlstra) >=20 > 2) Fix a MIPS related build problem (0day) >=20 > Other than that there are no changes and the other details are all the sa= me > as in V3 and V2. >=20 > It's also available from git: >=20 > git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git hotplug >=20 > Diff to V3 below. >=20 > Thanks, >=20 > tglx With this patchset: ``` [ 0.137719] smpboot: Allowing 32 CPUs, 0 hotplug CPUs [ 0.777312] smpboot: CPU0: AMD Ryzen 9 5950X 16-Core Processor (family: = 0x19, model: 0x21, stepping: 0x2) [ 0.777896] smpboot: Parallel CPU startup enabled: 0x80000000 ``` Seems to survive suspend/resume cycle too. Hence: Tested-by: Oleksandr Natalenko Thanks. > --- > diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c > index f5e0f4235746..90c71d800b59 100644 > --- a/arch/mips/kernel/smp.c > +++ b/arch/mips/kernel/smp.c > @@ -690,7 +690,7 @@ void flush_tlb_one(unsigned long vaddr) > EXPORT_SYMBOL(flush_tlb_page); > EXPORT_SYMBOL(flush_tlb_one); > =20 > -#ifdef CONFIG_HOTPLUG_CPU > +#ifdef CONFIG_HOTPLUG_CORE_SYNC_DEAD > void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) > { > if (mp_ops->cleanup_dead_cpu) > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 0438802031c3..9cd77d319555 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -290,8 +290,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) > =20 > /* APIC ID not found in the table. Drop the trampoline lock and bail. = */ > movq trampoline_lock(%rip), %rax > - lock > - btrl $0, (%rax) > + movl $0, (%rax) > =20 > 1: cli > hlt > @@ -320,8 +319,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) > movq trampoline_lock(%rip), %rax > testq %rax, %rax > jz .Lsetup_gdt > - lock > - btrl $0, (%rax) > + movl $0, (%rax) > =20 > .Lsetup_gdt: > /* > diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c > index 5caf4897b507..660709e94823 100644 > --- a/arch/x86/kernel/smpboot.c > +++ b/arch/x86/kernel/smpboot.c > @@ -161,31 +161,28 @@ static inline void smpboot_restore_warm_reset_vecto= r(void) > =20 > } > =20 > -/* > - * Report back to the Boot Processor during boot time or to the caller p= rocessor > - * during CPU online. > - */ > -static void smp_callin(void) > +/* Run the next set of setup steps for the upcoming CPU */ > +static void ap_starting(void) > { > int cpuid =3D smp_processor_id(); > =20 > /* > - * If waken up by an INIT in an 82489DX configuration the alive > - * synchronization guarantees we don't get here before an > - * INIT_deassert IPI reaches our local APIC, so it is now safe to > - * touch our local APIC. > + * If woken up by an INIT in an 82489DX configuration the alive > + * synchronization guarantees that the CPU does not reach this > + * point before an INIT_deassert IPI reaches the local APIC, so it > + * is now safe to touch the local APIC. > * > * Set up this CPU, first the APIC, which is probably redundant on > * most boards. > */ > apic_ap_setup(); > =20 > - /* Save our processor parameters. */ > + /* Save the processor parameters. */ > smp_store_cpu_info(cpuid); > =20 > /* > * The topology information must be up to date before > - * calibrate_delay() and notify_cpu_starting(). > + * notify_cpu_starting(). > */ > set_cpu_sibling_map(cpuid); > =20 > @@ -197,7 +194,7 @@ static void smp_callin(void) > =20 > /* > * This runs the AP through all the cpuhp states to its target > - * state (CPUHP_ONLINE in the case of serial bringup). > + * state CPUHP_ONLINE. > */ > notify_cpu_starting(cpuid); > } > @@ -274,10 +271,7 @@ static void notrace start_secondary(void *unused) > rcu_cpu_starting(raw_smp_processor_id()); > x86_cpuinit.early_percpu_clock_init(); > =20 > - smp_callin(); > - > - /* Otherwise gcc will move up smp_processor_id() before cpu_init() */ > - barrier(); > + ap_starting(); > =20 > /* Check TSC synchronization with the control CPU. */ > check_tsc_sync_target(); > diff --git a/arch/x86/realmode/rm/trampoline_64.S b/arch/x86/realmode/rm/= trampoline_64.S > index 2dfb1c400167..c6de4deec746 100644 > --- a/arch/x86/realmode/rm/trampoline_64.S > +++ b/arch/x86/realmode/rm/trampoline_64.S > @@ -40,17 +40,13 @@ > .macro LOAD_REALMODE_ESP > /* > * Make sure only one CPU fiddles with the realmode stack > - */ > + */ > .Llock_rm\@: > - btl $0, tr_lock > - jnc 2f > - pause > - jmp .Llock_rm\@ > + lock btsl $0, tr_lock > + jnc 2f > + pause > + jmp .Llock_rm\@ > 2: > - lock > - btsl $0, tr_lock > - jc .Llock_rm\@ > - > # Setup stack > movl $rm_stack_end, %esp > .endm > diff --git a/kernel/cpu.c b/kernel/cpu.c > index 60b4093fae9e..005f863a3d2b 100644 > --- a/kernel/cpu.c > +++ b/kernel/cpu.c > @@ -294,14 +294,14 @@ enum cpuhp_sync_state { > * cpuhp_ap_update_sync_state - Update synchronization state during brin= gup/teardown > * @state: The synchronization state to set > * > - * No synchronization point. Just update of the synchronization state. > + * No synchronization point. Just update of the synchronization state, b= ut implies > + * a full barrier so that the AP changes are visible before the control = CPU proceeds. > */ > static inline void cpuhp_ap_update_sync_state(enum cpuhp_sync_state stat= e) > { > atomic_t *st =3D this_cpu_ptr(&cpuhp_state.ap_sync_state); > - int sync =3D atomic_read(st); > =20 > - while (!atomic_try_cmpxchg(st, &sync, state)); > + (void)atomic_xchg(st, state); > } > =20 > void __weak arch_cpuhp_sync_state_poll(void) { cpu_relax(); } > @@ -829,7 +829,11 @@ static int bringup_cpu(unsigned int cpu) > /* > * Some architectures have to walk the irq descriptors to > * setup the vector space for the cpu which comes online. > - * Prevent irq alloc/free across the bringup. > + * > + * Prevent irq alloc/free across the bringup by acquiring the > + * sparse irq lock. Hold it until the upcoming CPU completes the > + * startup in cpuhp_online_idle() which allows to avoid > + * intermediate synchronization points in the architecture code. > */ > irq_lock_sparse(); > =20 >=20 >=20 >=20 =2D-=20 Oleksandr Natalenko (post-factum) From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67DABC77B7F for ; Sat, 13 May 2023 18:32:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X2j0ZaPcKiOEJ3KA1tXI8UaaEMbZPtyGKQAIcrBAooY=; b=4UHhtSNNkP4Xmc vWAL5GvQvNPlVaDNtNwf0LV8bbK4Gobjg9QoP8NXWn4BTp46UGcMU/DHW0AYzbSDbXIOYcQzCckik 0wUHMiMovb4pox2RgOmjisCNZu71nI8KTTnHg4P51H4DlA0GpZ6sLUFumbFawKpir8xXWxzA94XKA Vn1SwSHXdITOhfxNnH4ZiF3TlV/F+qH9jwprgBFjbogIOeiyOprjeb83VIb5nEvPpLICyCwypbBjC mHc9r/KCbfvVo5WwNYr50h5vyzpAaKgpOKV65M6HPkzNIHM9gW5DTJTSCSghkMb/IUeXa+hoO6esk zdTsuRJ/oqWMisLj8/ew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pxu2w-00FaRu-1y; Sat, 13 May 2023 18:32:46 +0000 Received: from vulcan.natalenko.name ([104.207.131.136]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pxu2s-00FaPE-1z; Sat, 13 May 2023 18:32:45 +0000 Received: from spock.localnet (unknown [83.148.33.151]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vulcan.natalenko.name (Postfix) with ESMTPSA id 3E98A130F201; Sat, 13 May 2023 20:32:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=natalenko.name; s=dkim-20170712; t=1684002754; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vRMdV3qzOVMwmQcnB02GoMJuuadMUEoFe1zlRRYP5Zw=; b=BYkiLxOIWN8IVtlF+nUBPTMaSvVLLm07F0DHp73Z+Eb7fP5wfHLu6+z3tHtGudVAjPmDGo cMZS4YuquHcnYJ9oS7feOQiSz26jdOO3YZzY3i1btzZDXY+EaLoZDj8CRG0dAnOPQirDG2 m5QBpNJvNrr34slkYe3VXn3/zoEgtxo= From: Oleksandr Natalenko To: LKML , Thomas Gleixner Cc: x86@kernel.org, David Woodhouse , Andrew Cooper , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Tom Lendacky , Sean Christopherson , Paul Menzel , "Guilherme G. Piccoli" , Piotr Gorski , Usama Arif , Juergen Gross , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E.J. 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