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Subject: Re: [loongson-PATCH-v2 23/23] Hibernation Support in mips system
From:	Wu Zhangjin <wuzhangjin@gmail.com>
Reply-To: wuzhangjin@gmail.com
To:	Arnaud Patard <apatard@mandriva.com>, huhb@lemote.com
Cc:	linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
	Yan Hua <yanh@lemote.com>,
	Philippe Vachon <philippe@cowpig.ca>,
	Zhang Le <r0bertz@gentoo.org>,
	Zhang Fuxin <zhangfx@lemote.com>,
	loongson-dev <loongson-dev@googlegroups.com>,
	Nicholas Mc Guire <der.herr@hofr.at>,
	Liu Junliang <liujl@lemote.com>,
	Erwan Lerale <erwan@thiscow.com>
In-Reply-To: <m3my8yoovk.fsf@anduin.mandriva.com>
References: <cover.1243362545.git.wuzj@lemote.com>
	 <1483a7cb0f587bd329ea3ca8d3af2881afadaf5e.1243362545.git.wuzj@lemote.com>
	 <m3my8yoovk.fsf@anduin.mandriva.com>
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Organization: DSLab, Lanzhou University, China
Date:	Thu, 28 May 2009 02:52:19 +0800
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Hi,

On Wed, 2009-05-27 at 11:51 +0200, Arnaud Patard wrote:
> > +LEAF(swsusp_arch_resume)
> > +	PTR_L t0, restore_pblist
> > +0:
> > +	PTR_L t1, PBE_ADDRESS(t0)   /* source */
> > +	PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
> > +	PTR_ADDIU t3, t1, _PAGE_SIZE
> > +1:
> > +	REG_L t8, (t1)
> > +	REG_S t8, (t2)
> > +	PTR_ADDIU t1, t1, SZREG
> > +	PTR_ADDIU t2, t2, SZREG
> > +	bne t1, t3, 1b
> > +	PTR_L t0, PBE_NEXT(t0)
> > +	bnez t0, 0b
> 
> you really need to flush cache/tlb here. If you don't do that you'll get
> some weird bugs.
> 

is this okay?

diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 9dbe48e..1f06fd5 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -2,6 +2,14 @@
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 #include <asm/asm.h>
+
+       .extern flush_cache_all
+#ifdef CONFIG_SMP
+       .extern flush_tlb_all
+#else
+       .extern local_flush_tlb_all
+#define flush_tlb_all local_flush_tlb_all
+#endif
 
 .text
 LEAF(swsusp_arch_suspend)
@@ -39,6 +47,16 @@ LEAF(swsusp_arch_resume)
        bne t1, t3, 1b
        PTR_L t0, PBE_NEXT(t0)
        bnez t0, 0b
+       /* flush caches to make sure context is in memory */
+       PTR_LA t1, flush_cache_all
+       PTR_L t0, 0(t1)
+       jalr t0
+       nop
+       /* flush tlb entries */
+       PTR_LA t1, flush_tlb_all
+       PTR_L t0, 0(t1)
+       jalr t0
+       nop
        PTR_LA t0, saved_regs
        PTR_L ra, PT_R31(t0)
        PTR_L sp, PT_R29(t0)

to Hongbing Hu,
 
    could you please help to test it? i do not have a Yeeloong laptop
currently. the above patch is applied to the latest git branch:
   
   git://dev.lemote.com/rt4ls.git linux-loongson-dev-to-ralf

thx!
Wu Zhangjin