From: sanguru <santoshguru@yahoo.com>
To: linuxppc-embedded@ozlabs.org
Subject: Enabling Cache in MPC5200
Date: Tue, 4 Sep 2007 01:22:03 -0700 (PDT) [thread overview]
Message-ID: <12473922.post@talk.nabble.com> (raw)
Hi,
I am using a LITE5200 evaluation board, and am not able to enable the
cache.
The execution hangs in these calls.
void EnableInstCache(void)
{
__asm(" mfspr r5,1008");
__asm(" ori r5,r5,0x00008800");// # Set the ICE and ICFI bit
__asm(" andi. r6,r5,0x0000F7FF");// # clear the ICFI bit for the
final store
__asm(" mtspr 1008,r5");
__asm(" isync");
__asm(" isync");
__asm(" isync");
__asm(" isync");
__asm(" sync");
__asm(" mtspr 1008,r6");// # Do the final store
__asm(" isync");
__asm(" sync");
}
void EnableDataCache(void)
{
__asm(" mfspr r5,1008");
__asm(" ori r5,r5,0x00004400");// # Set the ICE and ICFI bit
__asm(" andi. r6,r5,0x0000FBFF");// # clear the ICFI bit for the
final store
__asm(" mtspr 1008,r5");
__asm(" isync");
__asm(" isync");
__asm(" isync");
__asm(" isync");
__asm(" sync");
__asm(" mtspr 1008,r6");// # Do the final store
__asm(" isync");
__asm(" sync");
}
What could be the problem?
Thanks
-San
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View this message in context: http://www.nabble.com/Enabling-Cache-in-MPC5200-tf4376247.html#a12473922
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reply other threads:[~2007-09-04 8:22 UTC|newest]
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