From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 1/5] powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers
Date: Thu, 20 Aug 2009 10:43:48 +1000 [thread overview]
Message-ID: <1250729028.4810.42.camel@pasglop> (raw)
In-Reply-To: <AC207041-6DB9-476E-B171-C1F6E10D3FAB@kernel.crashing.org>
On Wed, 2009-08-19 at 16:37 -0500, Kumar Gala wrote:
> On Aug 19, 2009, at 2:25 AM, Benjamin Herrenschmidt wrote:
> The whole thing only ever gets called if we had tlbsrx. so is there
> any utility in making a part of conditional on tlbsrx?
I don't think so ... this is the second level TLB miss handler when
the first level takes a hit on the virtually linear page tables, I
has nothing to do with tlbsrx... however, it does offset the return
address back into the first level handler by -4 to account for
replaying the tlbsrx instruction which you probably don't want to do.
Ben.
next prev parent reply other threads:[~2009-08-20 0:43 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-08-19 5:08 [PATCH 1/5] powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers Kumar Gala
2009-08-19 5:08 ` [PATCH 2/5] powerpc/book3e-64: Move the default cpu table entry Kumar Gala
2009-08-19 5:08 ` [PATCH 3/5] powerpc/book3e-64: Wait til generic_calibrate_decr to enable decrementer Kumar Gala
2009-08-19 5:08 ` [PATCH 4/5] powerpc/book3e-64: Add helper function to setup IVORs Kumar Gala
2009-08-19 5:08 ` [PATCH 5/5] powerpc/book3e-64: Add support to initial_tlb_book3e for non-HES TLB Kumar Gala
2009-08-19 7:25 ` [PATCH 1/5] powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers Benjamin Herrenschmidt
2009-08-19 21:37 ` Kumar Gala
2009-08-20 0:43 ` Benjamin Herrenschmidt [this message]
2009-08-24 16:12 ` Kumar Gala
2009-08-25 1:08 ` Benjamin Herrenschmidt
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