--- irq.c	2009-09-21 19:24:30.000000000 -0500
+++ irq.c	2009-12-04 17:52:59.000000000 -0600
@@ -45,7 +45,8 @@
 
 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
 
-#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
+#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))  /* priority for interrupt chnl */
+#define LITTLE_TO_BIG_ENDIAN(i)  (24-(i)/8*8 + ((i)%8))  /* convert the bit number from little to big endin within 32 bit*/
 
 static void ar7_unmask_irq(unsigned int irq_nr);
 static void ar7_mask_irq(unsigned int irq_nr);
@@ -78,35 +79,35 @@
 
 static void ar7_unmask_irq(unsigned int irq)
 {
-	writel(1 << ((irq - ar7_irq_base) % 32),
+	writel(1<< LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base), 
 	       REG(ESR_OFFSET(irq - ar7_irq_base)));
 }
 
 static void ar7_mask_irq(unsigned int irq)
 {
-	writel(1 << ((irq - ar7_irq_base) % 32),
+	writel(1<< LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base),
 	       REG(ECR_OFFSET(irq - ar7_irq_base)));
 }
 
 static void ar7_ack_irq(unsigned int irq)
 {
-	writel(1 << ((irq - ar7_irq_base) % 32),
+	writel(1<<LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base),
 	       REG(CR_OFFSET(irq - ar7_irq_base)));
 }
 
 static void ar7_unmask_sec_irq(unsigned int irq)
 {
-	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
+	writel(1 << LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
 }
 
 static void ar7_mask_sec_irq(unsigned int irq)
 {
-	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
+	writel(1 << LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
 }
 
 static void ar7_ack_sec_irq(unsigned int irq)
 {
-	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
+	writel(1 << LITTLE_TO_BIG_ENDIAN(irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
 }
 
 void __init arch_init_irq(void)
@@ -123,16 +124,16 @@
 	 * Disable interrupts and clear pending
 	 */
 	writel(0xffffffff, REG(ECR_OFFSET(0)));
-	writel(0xff, REG(ECR_OFFSET(32)));
+	writel(0xff000000, REG(ECR_OFFSET(32)));
 	writel(0xffffffff, REG(SEC_ECR_OFFSET));
 	writel(0xffffffff, REG(CR_OFFSET(0)));
-	writel(0xff, REG(CR_OFFSET(32)));
+	writel(0xff000000, REG(CR_OFFSET(32)));
 	writel(0xffffffff, REG(SEC_CR_OFFSET));
 
 	ar7_irq_base = base;
 
 	for (i = 0; i < 40; i++) {
-		writel(i, REG(CHNL_OFFSET(i)));
+		writel(i<<24, REG(CHNL_OFFSET(i)));
 		/* Primary IRQ's */
 		set_irq_chip_and_handler(base + i, &ar7_irq_type,
 					 handle_edge_irq);
@@ -156,18 +157,18 @@
 	int i, irq;
 
 	/* Primary IRQ's */
-	irq = readl(REG(PIR_OFFSET)) & 0x3f;
+	irq = (readl(REG(PIR_OFFSET)) & 0x3f000000)>>24;
 	if (irq) {
 		do_IRQ(ar7_irq_base + irq);
 		return;
 	}
 
 	/* Secondary IRQ's are cascaded through primary '0' */
-	writel(1, REG(CR_OFFSET(irq)));
+	writel(0x01000000, REG(CR_OFFSET(irq)));
 	status = readl(REG(SEC_SR_OFFSET));
 	for (i = 0; i < 32; i++) {
 		if (status & 1) {
-			do_IRQ(ar7_irq_base + i + 40);
+			do_IRQ(ar7_irq_base + LITTLE_TO_BIG_ENDIAN(i) + 40);
 			return;
 		}
 		status >>= 1;