diff for duplicates of <1266433154.2322.0@antares> diff --git a/a/1.txt b/N1/1.txt index fa693fa..22717da 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -6,8 +6,7 @@ hangs resulting in timeouts: timeout occurs, and add a missing (required) MAL reset; 3. use a more reliable method to fixup the bus if a hang has been detected. The sequence is sent 9 times which seems to be necessary if a slave - "misses" more than one clock cycle. For 400 kHz bus speed, the fixup i= -s + "misses" more than one clock cycle. For 400 kHz bus speed, the fixup is also ~70us (81us vs. 150us) faster. Tested on a custom Lite5200b derived board, with a Dallas RTC, AD sensors @@ -15,29 +14,25 @@ and NXP IO expander chips attached to the i2c. Changes vs. v1: - use improved bus fixup sequence for all chips (not only the 5200) -- calculate real clock from defaults if no clock is given in the device tre= -e +- calculate real clock from defaults if no clock is given in the device tree - better description (I hope) of the changes. I didn't split the changes in this file into three parts as recommended by Grant, as they actually belong together (i.e. they address one single problem, just in three places of one single source file). -Signed-off-by: Albrecht Dre=DF <albrecht.dress@arcor.de> +Signed-off-by: Albrecht Dreß <albrecht.dress-KvP5wT2u2U0@public.gmane.org> --- -Note about the reset sequence: I verified the waveforms for 18.4kHz, 85.9kH= -z +Note about the reset sequence: I verified the waveforms for 18.4kHz, 85.9kHz and 375kHz (drop me a note if you want to see scope screen shots). Not verified on other mpc chips yet. @Ira: thanks in advance for giving it a try on your box! ---- linux-2.6.32-orig/drivers/i2c/busses/i2c-mpc.c 2009-12-03 04:51:21.0000= -00000 +0100 -+++ linux-2.6.32/drivers/i2c/busses/i2c-mpc.c 2010-02-17 16:23:11.000000000= - +0100 +--- linux-2.6.32-orig/drivers/i2c/busses/i2c-mpc.c 2009-12-03 04:51:21.000000000 +0100 ++++ linux-2.6.32/drivers/i2c/busses/i2c-mpc.c 2010-02-17 16:23:11.000000000 +0100 @@ -59,6 +59,7 @@ struct mpc_i2c { wait_queue_head_t queue; struct i2c_adapter adap; @@ -49,8 +44,7 @@ verified on other mpc chips yet. @@ -93,20 +94,23 @@ static irqreturn_t mpc_i2c_isr(int irq, /* Sometimes 9th clock pulse isn't generated, and slave doesn't release * the bus, because it wants to send ACK. - * Following sequence of enabling/disabling and sending start/stop genera= -tes + * Following sequence of enabling/disabling and sending start/stop generates - * the pulse, so it's all OK. + * the 9 pulses, so it's all OK. */ @@ -67,12 +61,12 @@ tes - writeccr(i2c, CCR_MEN); - udelay(30); + int k; -+ u32 delay_val =3D 1000000 / i2c->real_clk + 1; ++ u32 delay_val = 1000000 / i2c->real_clk + 1; + + if (delay_val < 2) -+ delay_val =3D 2; ++ delay_val = 2; + -+ for (k =3D 9; k; k--) { ++ for (k = 9; k; k--) { + writeccr(i2c, 0); + writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); + udelay(delay_val); @@ -86,32 +80,30 @@ tes {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} }; --int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescale= -r) -+int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescale= -r, +-int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) ++int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler, + u32 *real_clk) { - const struct mpc_i2c_divider *div =3D NULL; - unsigned int pvr =3D mfspr(SPRN_PVR); + const struct mpc_i2c_divider *div = NULL; + unsigned int pvr = mfspr(SPRN_PVR); u32 divider; int i; - if (!clock) + if (!clock) { -+ /* see below - default fdr =3D 0x3f -> div =3D 2048 */ -+ *real_clk =3D mpc5xxx_get_bus_frequency(node) / 2048; ++ /* see below - default fdr = 0x3f -> div = 2048 */ ++ *real_clk = mpc5xxx_get_bus_frequency(node) / 2048; return -EINVAL; + } /* Determine divider value */ - divider =3D mpc5xxx_get_bus_frequency(node) / clock; + divider = mpc5xxx_get_bus_frequency(node) / clock; @@ -212,7 +220,8 @@ int mpc_i2c_get_fdr_52xx(struct device_n break; } - return div ? (int)div->fdr : -EINVAL; -+ *real_clk =3D mpc5xxx_get_bus_frequency(node) / div->divider; ++ *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider; + return (int)div->fdr; } @@ -120,15 +112,15 @@ r, { int ret, fdr; -- ret =3D mpc_i2c_get_fdr_52xx(node, clock, prescaler); -+ ret =3D mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk); - fdr =3D (ret >=3D 0) ? ret : 0x3f; /* backward compatibility */ +- ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); ++ ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk); + fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); - if (ret >=3D 0) -- dev_info(i2c->dev, "clock %d Hz (fdr=3D%d)\n", clock, fdr); -+ dev_info(i2c->dev, "clock %u Hz (fdr=3D%d)\n", i2c->real_clk, + if (ret >= 0) +- dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); ++ dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk, + fdr); } #else /* !CONFIG_PPC_MPC52xx */ @@ -137,20 +129,18 @@ r, return val; } --int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescale= -r) -+int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescale= -r, +-int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) ++int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler, + u32 *real_clk) { - const struct mpc_i2c_divider *div =3D NULL; + const struct mpc_i2c_divider *div = NULL; u32 divider; int i; - if (!clock) + if (!clock) { -+ /* see below - default fdr =3D 0x1031 -> div =3D 16 * 3072 */ -+ *real_clk =3D fsl_get_sys_freq() / prescaler / (16 * 3072); ++ /* see below - default fdr = 0x1031 -> div = 16 * 3072 */ ++ *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072); return -EINVAL; + } @@ -160,7 +150,7 @@ r, break; } -+ *real_clk =3D fsl_get_sys_freq() / prescaler / div->divider; ++ *real_clk = fsl_get_sys_freq() / prescaler / div->divider; return div ? (int)div->fdr : -EINVAL; } @@ -168,15 +158,15 @@ r, { int ret, fdr; -- ret =3D mpc_i2c_get_fdr_8xxx(node, clock, prescaler); -+ ret =3D mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk); - fdr =3D (ret >=3D 0) ? ret : 0x1031; /* backward compatibility */ +- ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); ++ ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk); + fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); @@ -334,7 +349,7 @@ static void mpc_i2c_setclock_8xxx(struct - if (ret >=3D 0) - dev_info(i2c->dev, "clock %d Hz (dfsrr=3D%d fdr=3D%d)\n", + if (ret >= 0) + dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n", - clock, fdr >> 8, fdr & 0xff); + i2c->real_clk, fdr >> 8, fdr & 0xff); } @@ -186,12 +176,12 @@ r, return -EINTR; } if (time_after(jiffies, orig_jiffies + HZ)) { -+ u8 status =3D readb(i2c->base + MPC_I2C_SR); ++ u8 status = readb(i2c->base + MPC_I2C_SR); + dev_dbg(i2c->dev, "timeout\n"); -- if (readb(i2c->base + MPC_I2C_SR) =3D=3D +- if (readb(i2c->base + MPC_I2C_SR) == - (CSR_MCF | CSR_MBB | CSR_RXAK)) -+ if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) !=3D 0) { ++ if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) { + writeb(status & ~CSR_MAL, + i2c->base + MPC_I2C_SR); mpc_i2c_fixup(i2c); @@ -203,14 +193,14 @@ r, } } -+ prop =3D of_get_property(op->node, "fsl,timeout", &plen); -+ if (prop && plen =3D=3D sizeof(u32)) { -+ mpc_ops.timeout =3D *prop * HZ / 1000000; ++ prop = of_get_property(op->node, "fsl,timeout", &plen); ++ if (prop && plen == sizeof(u32)) { ++ mpc_ops.timeout = *prop * HZ / 1000000; + if (mpc_ops.timeout < 5) -+ mpc_ops.timeout =3D 5; ++ mpc_ops.timeout = 5; + } + dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); + dev_set_drvdata(&op->dev, i2c); - i2c->adap =3D mpc_ops; + i2c->adap = mpc_ops; diff --git a/a/content_digest b/N1/content_digest index 3cb2cd9..11ce940 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,11 +1,11 @@ - "From\0Albrecht Dre\303\237 <albrecht.dress@arcor.de>\0" + "From\0Albrecht Dre\303\237 <albrecht.dress-KvP5wT2u2U0@public.gmane.org>\0" "Subject\0[Patch v2 1/2] 5200/mpc: improve i2c bus error recovery\0" "Date\0Wed, 17 Feb 2010 19:59:14 +0100\0" - "To\0Linux PPC Development <linuxppc-dev@ozlabs.org>" - Devicetree Discussions <devicetree-discuss@lists.ozlabs.org> - Grant Likely <grant.likely@secretlab.ca> - " Ben Dooks (embedded platforms) <ben-linux@fluff.org>\0" - "Cc\0Ira W. Snyder <iws@ovro.caltech.edu>\0" + "To\0Linux PPC Development <linuxppc-dev-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>" + Devicetree Discussions <devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org> + Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> + " Ben Dooks (embedded platforms)\0" + "Cc\0Ira W. Snyder <iws-lulEs6mt1IksTUYHLfqkUA@public.gmane.org>\0" "\00:1\0" "b\0" "This patch improves the recovery of the MPC's I2C bus from errors like bus\n" @@ -16,8 +16,7 @@ " timeout occurs, and add a missing (required) MAL reset;\n" "3. use a more reliable method to fixup the bus if a hang has been detected.\n" " The sequence is sent 9 times which seems to be necessary if a slave\n" - " \"misses\" more than one clock cycle. For 400 kHz bus speed, the fixup i=\n" - "s\n" + " \"misses\" more than one clock cycle. For 400 kHz bus speed, the fixup is\n" " also ~70us (81us vs. 150us) faster.\n" "\n" "Tested on a custom Lite5200b derived board, with a Dallas RTC, AD sensors\n" @@ -25,29 +24,25 @@ "\n" "Changes vs. v1:\n" "- use improved bus fixup sequence for all chips (not only the 5200)\n" - "- calculate real clock from defaults if no clock is given in the device tre=\n" - "e\n" + "- calculate real clock from defaults if no clock is given in the device tree\n" "- better description (I hope) of the changes.\n" "\n" "I didn't split the changes in this file into three parts as recommended by\n" "Grant, as they actually belong together (i.e. they address one single\n" "problem, just in three places of one single source file).\n" "\n" - "Signed-off-by: Albrecht Dre=DF <albrecht.dress@arcor.de>\n" + "Signed-off-by: Albrecht Dre\303\237 <albrecht.dress-KvP5wT2u2U0@public.gmane.org>\n" "\n" "---\n" "\n" - "Note about the reset sequence: I verified the waveforms for 18.4kHz, 85.9kH=\n" - "z\n" + "Note about the reset sequence: I verified the waveforms for 18.4kHz, 85.9kHz\n" "and 375kHz (drop me a note if you want to see scope screen shots). Not\n" "verified on other mpc chips yet.\n" "@Ira: thanks in advance for giving it a try on your box!\n" "\n" "\n" - "--- linux-2.6.32-orig/drivers/i2c/busses/i2c-mpc.c\t2009-12-03 04:51:21.0000=\n" - "00000 +0100\n" - "+++ linux-2.6.32/drivers/i2c/busses/i2c-mpc.c\t2010-02-17 16:23:11.000000000=\n" - " +0100\n" + "--- linux-2.6.32-orig/drivers/i2c/busses/i2c-mpc.c\t2009-12-03 04:51:21.000000000 +0100\n" + "+++ linux-2.6.32/drivers/i2c/busses/i2c-mpc.c\t2010-02-17 16:23:11.000000000 +0100\n" "@@ -59,6 +59,7 @@ struct mpc_i2c {\n" " \twait_queue_head_t queue;\n" " \tstruct i2c_adapter adap;\n" @@ -59,8 +54,7 @@ "@@ -93,20 +94,23 @@ static irqreturn_t mpc_i2c_isr(int irq,\n" " /* Sometimes 9th clock pulse isn't generated, and slave doesn't release\n" " * the bus, because it wants to send ACK.\n" - " * Following sequence of enabling/disabling and sending start/stop genera=\n" - "tes\n" + " * Following sequence of enabling/disabling and sending start/stop generates\n" "- * the pulse, so it's all OK.\n" "+ * the 9 pulses, so it's all OK.\n" " */\n" @@ -77,12 +71,12 @@ "-\twriteccr(i2c, CCR_MEN);\n" "-\tudelay(30);\n" "+\tint k;\n" - "+\tu32 delay_val =3D 1000000 / i2c->real_clk + 1;\n" + "+\tu32 delay_val = 1000000 / i2c->real_clk + 1;\n" "+\n" "+\tif (delay_val < 2)\n" - "+\t\tdelay_val =3D 2;\n" + "+\t\tdelay_val = 2;\n" "+\n" - "+\tfor (k =3D 9; k; k--) {\n" + "+\tfor (k = 9; k; k--) {\n" "+\t\twriteccr(i2c, 0);\n" "+\t\twriteccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);\n" "+\t\tudelay(delay_val);\n" @@ -96,32 +90,30 @@ " \t{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}\n" " };\n" "\n" - "-int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescale=\n" - "r)\n" - "+int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescale=\n" - "r,\n" + "-int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)\n" + "+int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler,\n" "+\t\t\t u32 *real_clk)\n" " {\n" - " \tconst struct mpc_i2c_divider *div =3D NULL;\n" - " \tunsigned int pvr =3D mfspr(SPRN_PVR);\n" + " \tconst struct mpc_i2c_divider *div = NULL;\n" + " \tunsigned int pvr = mfspr(SPRN_PVR);\n" " \tu32 divider;\n" " \tint i;\n" "\n" "-\tif (!clock)\n" "+\tif (!clock) {\n" - "+\t\t/* see below - default fdr =3D 0x3f -> div =3D 2048 */\n" - "+\t\t*real_clk =3D mpc5xxx_get_bus_frequency(node) / 2048;\n" + "+\t\t/* see below - default fdr = 0x3f -> div = 2048 */\n" + "+\t\t*real_clk = mpc5xxx_get_bus_frequency(node) / 2048;\n" " \t\treturn -EINVAL;\n" "+\t}\n" "\n" " \t/* Determine divider value */\n" - " \tdivider =3D mpc5xxx_get_bus_frequency(node) / clock;\n" + " \tdivider = mpc5xxx_get_bus_frequency(node) / clock;\n" "@@ -212,7 +220,8 @@ int mpc_i2c_get_fdr_52xx(struct device_n\n" " \t\t\tbreak;\n" " \t}\n" "\n" "-\treturn div ? (int)div->fdr : -EINVAL;\n" - "+\t*real_clk =3D mpc5xxx_get_bus_frequency(node) / div->divider;\n" + "+\t*real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;\n" "+\treturn (int)div->fdr;\n" " }\n" "\n" @@ -130,15 +122,15 @@ " {\n" " \tint ret, fdr;\n" "\n" - "-\tret =3D mpc_i2c_get_fdr_52xx(node, clock, prescaler);\n" - "+\tret =3D mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);\n" - " \tfdr =3D (ret >=3D 0) ? ret : 0x3f; /* backward compatibility */\n" + "-\tret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);\n" + "+\tret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);\n" + " \tfdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */\n" "\n" " \twriteb(fdr & 0xff, i2c->base + MPC_I2C_FDR);\n" "\n" - " \tif (ret >=3D 0)\n" - "-\t\tdev_info(i2c->dev, \"clock %d Hz (fdr=3D%d)\\n\", clock, fdr);\n" - "+\t\tdev_info(i2c->dev, \"clock %u Hz (fdr=3D%d)\\n\", i2c->real_clk,\n" + " \tif (ret >= 0)\n" + "-\t\tdev_info(i2c->dev, \"clock %d Hz (fdr=%d)\\n\", clock, fdr);\n" + "+\t\tdev_info(i2c->dev, \"clock %u Hz (fdr=%d)\\n\", i2c->real_clk,\n" "+\t\t\t fdr);\n" " }\n" " #else /* !CONFIG_PPC_MPC52xx */\n" @@ -147,20 +139,18 @@ " \treturn val;\n" " }\n" "\n" - "-int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescale=\n" - "r)\n" - "+int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescale=\n" - "r,\n" + "-int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)\n" + "+int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler,\n" "+\t\t\t u32 *real_clk)\n" " {\n" - " \tconst struct mpc_i2c_divider *div =3D NULL;\n" + " \tconst struct mpc_i2c_divider *div = NULL;\n" " \tu32 divider;\n" " \tint i;\n" "\n" "-\tif (!clock)\n" "+\tif (!clock) {\n" - "+\t\t/* see below - default fdr =3D 0x1031 -> div =3D 16 * 3072 */\n" - "+\t\t*real_clk =3D fsl_get_sys_freq() / prescaler / (16 * 3072);\n" + "+\t\t/* see below - default fdr = 0x1031 -> div = 16 * 3072 */\n" + "+\t\t*real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);\n" " \t\treturn -EINVAL;\n" "+\t}\n" "\n" @@ -170,7 +160,7 @@ " \t\t\tbreak;\n" " \t}\n" "\n" - "+\t*real_clk =3D fsl_get_sys_freq() / prescaler / div->divider;\n" + "+\t*real_clk = fsl_get_sys_freq() / prescaler / div->divider;\n" " \treturn div ? (int)div->fdr : -EINVAL;\n" " }\n" "\n" @@ -178,15 +168,15 @@ " {\n" " \tint ret, fdr;\n" "\n" - "-\tret =3D mpc_i2c_get_fdr_8xxx(node, clock, prescaler);\n" - "+\tret =3D mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);\n" - " \tfdr =3D (ret >=3D 0) ? ret : 0x1031; /* backward compatibility */\n" + "-\tret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);\n" + "+\tret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);\n" + " \tfdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */\n" "\n" " \twriteb(fdr & 0xff, i2c->base + MPC_I2C_FDR);\n" "@@ -334,7 +349,7 @@ static void mpc_i2c_setclock_8xxx(struct\n" "\n" - " \tif (ret >=3D 0)\n" - " \t\tdev_info(i2c->dev, \"clock %d Hz (dfsrr=3D%d fdr=3D%d)\\n\",\n" + " \tif (ret >= 0)\n" + " \t\tdev_info(i2c->dev, \"clock %d Hz (dfsrr=%d fdr=%d)\\n\",\n" "-\t\t\t clock, fdr >> 8, fdr & 0xff);\n" "+\t\t\t i2c->real_clk, fdr >> 8, fdr & 0xff);\n" " }\n" @@ -196,12 +186,12 @@ " \t\t\treturn -EINTR;\n" " \t\t}\n" " \t\tif (time_after(jiffies, orig_jiffies + HZ)) {\n" - "+\t\t\tu8 status =3D readb(i2c->base + MPC_I2C_SR);\n" + "+\t\t\tu8 status = readb(i2c->base + MPC_I2C_SR);\n" "+\n" " \t\t\tdev_dbg(i2c->dev, \"timeout\\n\");\n" - "-\t\t\tif (readb(i2c->base + MPC_I2C_SR) =3D=3D\n" + "-\t\t\tif (readb(i2c->base + MPC_I2C_SR) ==\n" "-\t\t\t (CSR_MCF | CSR_MBB | CSR_RXAK))\n" - "+\t\t\tif ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) !=3D 0) {\n" + "+\t\t\tif ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {\n" "+\t\t\t\twriteb(status & ~CSR_MAL,\n" "+\t\t\t\t i2c->base + MPC_I2C_SR);\n" " \t\t\t\tmpc_i2c_fixup(i2c);\n" @@ -213,16 +203,16 @@ " \t\t}\n" " \t}\n" "\n" - "+\tprop =3D of_get_property(op->node, \"fsl,timeout\", &plen);\n" - "+\tif (prop && plen =3D=3D sizeof(u32)) {\n" - "+\t\tmpc_ops.timeout =3D *prop * HZ / 1000000;\n" + "+\tprop = of_get_property(op->node, \"fsl,timeout\", &plen);\n" + "+\tif (prop && plen == sizeof(u32)) {\n" + "+\t\tmpc_ops.timeout = *prop * HZ / 1000000;\n" "+\t\tif (mpc_ops.timeout < 5)\n" - "+\t\t\tmpc_ops.timeout =3D 5;\n" + "+\t\t\tmpc_ops.timeout = 5;\n" "+\t}\n" "+\tdev_info(i2c->dev, \"timeout %u us\\n\", mpc_ops.timeout * 1000000 / HZ);\n" "+\n" " \tdev_set_drvdata(&op->dev, i2c);\n" "\n" - " \ti2c->adap =3D mpc_ops;" + " \ti2c->adap = mpc_ops;" -3e773714f91ed6ef9c5ebb29f456843741768b92107c235e02e4576fcccd2a09 +4d7e5ed8c65ddcd265fca2fb6d88c23b1d64ba9d131b45793b31cd6bbe4e809f
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