Re: Freescale P2020 / 85xx PCIe and Advance Error Reporting (AER) service problem

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

> BUT if we take into consideration that:
> 1. Freescale is a serious dude in the hood and on the whole does a good 
> job with its products and their Linux support.

Sure but that's irrelevant to the technical problem at hand :-)

> 2. The P2020 does state it has an MSI mechanism support (although one is 
> not present as a PCIe capability header for some reason)

Then it's broken :-(

> 3. Errors in general and AER are major features in PCIe.
> 4. PCIe has been here quite a while and it is not new to Freescale or 
> anyone else.

Right but we don't do AER on ppc44x either, I know we should but for
some reason, AER hasn't been on anybody #1 priority list in embedded
world so far...

> I am much more inclined to believe that I have missed something by a 
> mile then that Freescale did. I just don't know what I am missing.

No, I think you haven't and we just need to fix it :-)

Cheers,
Ben.

> My device tree is a clone of "arch/ powerpc/ boot/ dts/ p2020rdb.dts"
> 
> It has a PCI node that looks like this:
> ----------------------------- snip -----------------------------
>     pci0: pcie@ffe09000 {
>         cell-index = <1>;
>         compatible = "fsl,mpc8548-pcie";
>         device_type = "pci";
>         #interrupt-cells = <1>;
>         #size-cells = <2>;
>         #address-cells = <3>;
>         reg = <0 0xffe09000 0 0x1000>;
>         bus-range = <0 255>;
>         ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
>               0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
>         clock-frequency = <33333333>;
>         interrupt-parent = <&mpic>;
>         interrupts = <25 2>;
>         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
>         interrupt-map = <
>             /* IDSEL 0x0 */
>             0000 0x0 0x0 0x1 &mpic 0x4 0x1
>             0000 0x0 0x0 0x2 &mpic 0x5 0x1
>             0000 0x0 0x0 0x3 &mpic 0x6 0x1
>             0000 0x0 0x0 0x4 &mpic 0x7 0x1
>             >;
>         pcie@0 {
>             reg = <0x0 0x0 0x0 0x0 0x0>;
>             #size-cells = <2>;
>             #address-cells = <3>;
>             device_type = "pci";
>             ranges = <0x2000000 0x0 0xa0000000
>                   0x2000000 0x0 0xa0000000
>                   0x0 0x20000000
> 
>                   0x1000000 0x0 0x0
>                   0x1000000 0x0 0x0
>                   0x0 0x100000>;
>         };
>     };
> ----------------------------- snap -----------------------------
> 
> and under "soc" it has an MSI node that looks like that:
> ----------------------------- snip -----------------------------
>         msi@41600 {
>             compatible = "fsl,p2020-msi", "fsl,mpic-msi";
>             reg = <0x41600 0x80>;
>             msi-available-ranges = <0 0x100>;
>             interrupts = <
>                 0xe0 0
>                 0xe1 0
>                 0xe2 0
>                 0xe3 0
>                 0xe4 0
>                 0xe5 0
>                 0xe6 0
>                 0xe7 0>;
>             interrupt-parent = <&mpic>;
>         };
> ----------------------------- snap -----------------------------
> 
> -- Liberty
>