From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Clifton Subject: Re: Corruption in glxgears with Compiz Date: Sat, 23 Oct 2010 19:33:45 +0100 Message-ID: <1287858825.4513.3.camel@pcjc2lap> References: <1287751996.19922.4.camel@pcjc2lap> <849307$a3hfvt@azsmga001.ch.intel.com> <1287774644.17191.9.camel@pcjc2lap> <5b55a1$ien4q1@fmsmga002.fm.intel.com> <1287804946.9701.3.camel@pcjc2lap> <1287806877.2423.3.camel@pcjc2lap> <1287834125.2578.6.camel@pcjc2lap> <5b55a1$ietjas@fmsmga002.fm.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from ppsw-51.csi.cam.ac.uk (ppsw-51.csi.cam.ac.uk [131.111.8.151]) by gabe.freedesktop.org (Postfix) with ESMTP id 838199E758 for ; Sat, 23 Oct 2010 11:33:47 -0700 (PDT) In-Reply-To: <5b55a1$ietjas@fmsmga002.fm.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Sat, 2010-10-23 at 18:48 +0100, Chris Wilson wrote: > We're always eager to improve our code to get the most of our admittedly > lack-luster GPUs. Even suggests on what tools would be useful or > improvements we could make to improve profiling/development are most > welcome. One thing I was wondering about, was intel_gpu_top. It reports unit usage based on busy / done registers in the chip. I wondered what would happen if we polled those registers and graphed them in time... whether it would show any hints as to which units were waiting on each other, and where any gaps are. It would need to be graphical probably, and it would need to be synchronised in some way to the application / frames being processed, so all in all, it is rather hard to imagine how it would work with perhaps unrelated GPU activity going on for other things such as the compositor and toolkit redrawing. I sometimes wonder if it is just memory bandwidth constraining things.. perhaps I need to look to the chipset docs and see if there are any performance diagnostic regs there as well. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)