Re: [PATCH] intel: Fix emit_linear_blit to use DWORD aligned width blits

[Peter Clifton <pcjc2@cam.ac.uk>]

On Sun, 2010-11-07 at 10:25 +0000, Chris Wilson wrote:
> On Sat, 06 Nov 2010 10:04:31 +0000, Peter Clifton <pcjc2@cam.ac.uk> wrote:
> > Fixes corruption with glBufferSubData on my machine,
> > 
> > Can someone review and push?
> 
> Oddly, the pitch for BLT is in bytes and it should be sufficient to be a
> multiple of element-size. Or two element-size depending on circumstances. 
> 
> Just to satisfy my curiosity, what happens with (1<<15 - 2)?

I've not tried that yet, but the PRM does state that BLT pitch is in
DWORDs.


We do this:

   src_pitch *= cpp;
   dst_pitch *= cpp;

Converting a pitch passed to the blit function in _pixels_, to a pitch
in bytes, but further dragons lurking I think:

Also, only on non I915 defined builds of intel_blit.c, we also do things
like:

   if (dst_tiling != I915_TILING_NONE) {
      CMD |= XY_DST_TILED;
      dst_pitch /= 4;
   }


The G45 PRM doesn't appear to specify pitch is in DWORDS _only_ for
tiled surfaces, merely that there is further restriction:

"
Source Pitch (double word aligned) and in DWords: [15:00] 2’s
complement.

For Tiled Src (bit 15 enabled) this pitch is of 512Byte granularity and
can be upto 128Kbytes (or 32KDwords).
"

Truthfully, I'm not quite sure I understand what the implication for a
tiled surface is.. or how pitch should be calculated correctly for that
case.. but it does seem clear that our handing for non-tiled surfaces is
suspect.


-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)

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