From: Vasanthakumar Thiagarajan <vasanth@atheros.com>
To: <linville@tuxdriver.com>
Cc: <linux-wireless@vger.kernel.org>
Subject: [PATCH V2 04/27] ath9k_hw: Initialize mode registers for AR9485
Date: Thu, 2 Dec 2010 03:06:48 -0800 [thread overview]
Message-ID: <1291288031-3409-5-git-send-email-vasanth@atheros.com> (raw)
In-Reply-To: <1291288031-3409-1-git-send-email-vasanth@atheros.com>
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
---
drivers/net/wireless/ath/ath9k/ar9003_hw.c | 195 ++++++++++++++++++----------
1 files changed, 129 insertions(+), 66 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 0e3e259..f01c289 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -17,6 +17,7 @@
#include "hw.h"
#include "ar9003_mac.h"
#include "ar9003_2p2_initvals.h"
+#include "ar9485_initvals.h"
/* General hardware code for the AR9003 hadware family */
@@ -39,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
*/
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
{
- /* mac */
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
- ar9300_2p2_mac_core,
- ARRAY_SIZE(ar9300_2p2_mac_core), 2);
- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
- ar9300_2p2_mac_postamble,
- ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
-
- /* bb */
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
- ar9300_2p2_baseband_core,
- ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
- ar9300_2p2_baseband_postamble,
- ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
-
- /* radio */
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
- ar9300_2p2_radio_core,
- ARRAY_SIZE(ar9300_2p2_radio_core), 2);
- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
- ar9300_2p2_radio_postamble,
- ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
-
- /* soc */
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
- ar9300_2p2_soc_preamble,
- ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
- ar9300_2p2_soc_postamble,
- ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
-
- /* rx/tx gain */
- INIT_INI_ARRAY(&ah->iniModesRxGain,
- ar9300Common_rx_gain_table_2p2,
- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
- INIT_INI_ARRAY(&ah->iniModesTxGain,
- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
- 5);
-
- /* Load PCIE SERDES settings from INI */
-
- /* Awake Setting */
-
- INIT_INI_ARRAY(&ah->iniPcieSerdes,
- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
- 2);
-
- /* Sleep Setting */
-
- INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
- ar9300PciePhy_clkreq_enable_L1_2p2,
- ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
- 2);
-
- /* Fast clock modal settings */
- INIT_INI_ARRAY(&ah->iniModesAdditional,
- ar9300Modes_fast_clock_2p2,
- ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
- 3);
+ if (AR_SREV_9485(ah)) {
+ /* mac */
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+ ar9485_1_0_mac_core,
+ ARRAY_SIZE(ar9485_1_0_mac_core), 2);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+ ar9485_1_0_mac_postamble,
+ ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
+
+ /* bb */
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
+ ARRAY_SIZE(ar9485_1_0), 2);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+ ar9485_1_0_baseband_core,
+ ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+ ar9485_1_0_baseband_postamble,
+ ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
+
+ /* radio */
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+ ar9485_1_0_radio_core,
+ ARRAY_SIZE(ar9485_1_0_radio_core), 2);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+ ar9485_1_0_radio_postamble,
+ ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+ ar9485_1_0_soc_preamble,
+ ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9485Common_rx_gain_1_0,
+ ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9485Modes_lowest_ob_db_tx_gain_1_0,
+ ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+ 5);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+ ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
+ ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
+ 2);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+ ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
+ ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
+ 2);
+ } else {
+ /* mac */
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+ ar9300_2p2_mac_core,
+ ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+ ar9300_2p2_mac_postamble,
+ ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+
+ /* bb */
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+ ar9300_2p2_baseband_core,
+ ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+ ar9300_2p2_baseband_postamble,
+ ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+
+ /* radio */
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+ ar9300_2p2_radio_core,
+ ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+ ar9300_2p2_radio_postamble,
+ ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+ ar9300_2p2_soc_preamble,
+ ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+ ar9300_2p2_soc_postamble,
+ ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+ ar9300Common_rx_gain_table_2p2,
+ ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+ ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+ ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+ 5);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+ ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+ 2);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+ ar9300PciePhy_clkreq_enable_L1_2p2,
+ ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+ 2);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesAdditional,
+ ar9300Modes_fast_clock_2p2,
+ ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+ 3);
+ }
}
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
--
1.7.0.4
next prev parent reply other threads:[~2010-12-02 11:09 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-02 11:06 [PATCH V2 00/27] Add support for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 01/27] ath9k_hw: Define hw version macros " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 02/27] ath9k_hw: Add initvals.h " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 03/27] ath9k_hw: Enable hw initialization " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` Vasanthakumar Thiagarajan [this message]
2010-12-02 11:06 ` [PATCH V2 05/27] ath9k_hw: Initialize tx/rx gain table from initvals.h " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 06/27] ath9k_hw: Eeeprom changes " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 07/27] ath9k_hw: Disable LDPC " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 08/27] ath9k: Disable TX STBC " Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 09/27] ath9k: Enable extended synch for AR9485 to fix L0s recovery issue Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 10/27] ath9k_hw: Find the maximum number of chains that hw supports Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 11/27] ath9k_hw: Configure pll control for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 12/27] ath9k_hw: Find chansel of AR_PHY_65NM_CH0_SYNTH7 from an array " Vasanthakumar Thiagarajan
2010-12-03 1:45 ` Felix Fietkau
2010-12-03 4:50 ` Vasanthakumar Thiagarajan
2010-12-03 12:14 ` Felix Fietkau
2010-12-03 12:40 ` Vasanthakumar Thiagarajan
2010-12-03 12:48 ` Felix Fietkau
2010-12-06 6:03 ` Vasanthakumar Thiagarajan
2010-12-06 10:42 ` Felix Fietkau
2010-12-06 11:44 ` Vasanthakumar Thiagarajan
2010-12-06 11:50 ` Felix Fietkau
2010-12-06 11:54 ` Vasanthakumar Thiagarajan
2010-12-06 11:51 ` Johannes Berg
2010-12-02 11:06 ` [PATCH V2 13/27] ath9k_hw: Add a helper function to get spur channel pointer from cal data for AR9003 family Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 14/27] ath9k_hw: Read spur channel information from eeprom for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:06 ` [PATCH V2 15/27] ath9k_hw: Configure xpa bias level " Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 16/27] ath9k_hw: Read and configure antenna diversity control " Vasanthakumar Thiagarajan
2010-12-02 11:22 ` Julian Calaby
2010-12-02 12:09 ` Vasanthakumar Thiagarajan
2010-12-02 12:16 ` Julian Calaby
2010-12-02 12:21 ` Vasanthakumar Thiagarajan
2010-12-02 12:29 ` Julian Calaby
2010-12-02 11:07 ` [PATCH V2 17/27] ath9k_hw: Configure attenuation control only for supported chains Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 18/27] ath9k_hw: Configure internal regulator for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 19/27] ath9k_hw: Read and configure turnning caps to regulate freq accuracy Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 20/27] ath9k_hw: Configure power control only for the supported chains Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 21/27] ath9k_hw: Program appropriate chianmask for AR9485 before starting AGC/IQ cal Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 22/27] ath9k_hw: Define IQcal correction coefficient registers using index Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 23/27] ath9k_hw: Add IQ cal changes for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 24/27] ath9k_hw: Program appropriate register for temperature compensation cal " Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 25/27] ath9k_hw: Setup paprd only for supported chains Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 26/27] ath9k_hw: Disable MRC CCK for AR9485 Vasanthakumar Thiagarajan
2010-12-02 11:07 ` [PATCH V2 27/27] ath9k: Add device id of AR9485 to pci table Vasanthakumar Thiagarajan
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